%0 Conference Paper
%A Difronzo, Michele
%A Ginn, Herbert L.
%A Benigni, Andrea
%T A Low Latency Parallel Bus Interface for High-Speed multi-FPGA RT-Simulations
%I IEEE
%M FZJ-2023-01343
%P 7
%D 2021
%< 2021 IEEE Electric Ship Technologies Symposium (ESTS) : [Proceedings] - IEEE, 2021. - ISBN 978-1-7281-8426-5 - doi:10.1109/ESTS49166.2021.9512344
%B 2021 IEEE Electric Ship Technologies Symposium (ESTS)
%C 3 Aug 2021 - 6 Aug 2021, Arlington (VA)
Y2 3 Aug 2021 - 6 Aug 2021
M2 Arlington, VA
%F PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
%9 Contribution to a conference proceedingsContribution to a book
%U <Go to ISI:>//WOS:000701617100031
%R 10.1109/ESTS49166.2021.9512344
%U https://juser.fz-juelich.de/record/1005155