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@ARTICLE{Bengel:1007139,
      author       = {Bengel, Christopher and Dixius, Leon and Waser, R. and
                      Wouters, Dirk J. and Menzel, Stephan},
      title        = {{B}it slicing approaches for variability aware {R}e{RAM}
                      {CIM} macros},
      journal      = {Information technology},
      volume       = {0},
      number       = {0},
      issn         = {0013-5720},
      address      = {Berlin},
      publisher    = {˜Deœ Gruyter},
      reportid     = {FZJ-2023-01963},
      pages        = {1},
      year         = {2023},
      abstract     = {Computation-in-Memory accelerators based on resistive
                      switching devices represent a promising approach to realize
                      future information processing systems. These architectures
                      promise orders of magnitudes lower energy consumption for
                      certain tasks, while also achieving higher throughputs than
                      other special purpose hardware such as GPUs, due to their
                      analog computation nature. Due to device variability issues,
                      however, a single resistive switching cell usually does not
                      achieve the resolution required for the considered
                      applications. To overcome this challenge, many of the
                      proposed architectures use an approach called bit slicing,
                      where generally multiple low-resolution components are
                      combined to realize higher resolution blocks. In this paper,
                      we will present an analog accelerator architecture on the
                      circuit level, which can be used to perform
                      Vector-Matrix-Multiplications or
                      Matrix-Matrix-Multiplications. The architecture consists of
                      the 1T1R crossbar array, the optimized select circuitry and
                      an ADC. The components are designed to handle the
                      variability of the resistive switching cells, which is
                      verified through our verified and physical compact model. We
                      then use this architecture to compare different bit slicing
                      approaches and discuss their tradeoffs.},
      cin          = {PGI-7 / PGI-10 / JARA-FIT},
      ddc          = {620},
      cid          = {I:(DE-Juel1)PGI-7-20110106 / I:(DE-Juel1)PGI-10-20170113 /
                      $I:(DE-82)080009_20140620$},
      pnm          = {5233 - Memristive Materials and Devices (POF4-523) / BMBF
                      16ME0399 - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0399) / BMBF 16ME0398K -
                      Verbundprojekt: Neuro-inspirierte Technologien der
                      künstlichen Intelligenz für die Elektronik der Zukunft -
                      NEUROTEC II - (BMBF-16ME0398K) / DFG project 167917811 - SFB
                      917: Resistiv schaltende Chalkogenide für zukünftige
                      Elektronikanwendungen: Struktur, Kinetik und
                      Bauelementskalierung "Nanoswitches" (167917811)},
      pid          = {G:(DE-HGF)POF4-5233 / G:(DE-82)BMBF-16ME0399 /
                      G:(DE-82)BMBF-16ME0398K / G:(GEPRIS)167917811},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000976053800001},
      doi          = {10.1515/itit-2023-0018},
      url          = {https://juser.fz-juelich.de/record/1007139},
}