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| 001 | 1007139 | ||
| 005 | 20230929112527.0 | ||
| 024 | 7 | _ | |a 10.1515/itit-2023-0018 |2 doi |
| 024 | 7 | _ | |a 0013-5720 |2 ISSN |
| 024 | 7 | _ | |a 0179-9738 |2 ISSN |
| 024 | 7 | _ | |a 0944-2774 |2 ISSN |
| 024 | 7 | _ | |a 1611-2776 |2 ISSN |
| 024 | 7 | _ | |a 2196-7032 |2 ISSN |
| 024 | 7 | _ | |a 2128/34438 |2 Handle |
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| 037 | _ | _ | |a FZJ-2023-01963 |
| 082 | _ | _ | |a 620 |
| 100 | 1 | _ | |a Bengel, Christopher |0 P:(DE-Juel1)188159 |b 0 |
| 245 | _ | _ | |a Bit slicing approaches for variability aware ReRAM CIM macros |
| 260 | _ | _ | |a Berlin |c 2023 |b De Gruyter |
| 336 | 7 | _ | |a article |2 DRIVER |
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| 520 | _ | _ | |a Computation-in-Memory accelerators based on resistive switching devices represent a promising approach to realize future information processing systems. These architectures promise orders of magnitudes lower energy consumption for certain tasks, while also achieving higher throughputs than other special purpose hardware such as GPUs, due to their analog computation nature. Due to device variability issues, however, a single resistive switching cell usually does not achieve the resolution required for the considered applications. To overcome this challenge, many of the proposed architectures use an approach called bit slicing, where generally multiple low-resolution components are combined to realize higher resolution blocks. In this paper, we will present an analog accelerator architecture on the circuit level, which can be used to perform Vector-Matrix-Multiplications or Matrix-Matrix-Multiplications. The architecture consists of the 1T1R crossbar array, the optimized select circuitry and an ADC. The components are designed to handle the variability of the resistive switching cells, which is verified through our verified and physical compact model. We then use this architecture to compare different bit slicing approaches and discuss their tradeoffs. |
| 536 | _ | _ | |a 5233 - Memristive Materials and Devices (POF4-523) |0 G:(DE-HGF)POF4-5233 |c POF4-523 |f POF IV |x 0 |
| 536 | _ | _ | |a BMBF 16ME0399 - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0399) |0 G:(DE-82)BMBF-16ME0399 |c BMBF-16ME0399 |x 1 |
| 536 | _ | _ | |a BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K) |0 G:(DE-82)BMBF-16ME0398K |c BMBF-16ME0398K |x 2 |
| 536 | _ | _ | |a DFG project 167917811 - SFB 917: Resistiv schaltende Chalkogenide für zukünftige Elektronikanwendungen: Struktur, Kinetik und Bauelementskalierung "Nanoswitches" (167917811) |0 G:(GEPRIS)167917811 |c 167917811 |x 3 |
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| 700 | 1 | _ | |a Dixius, Leon |0 P:(DE-HGF)0 |b 1 |
| 700 | 1 | _ | |a Waser, R. |0 P:(DE-Juel1)131022 |b 2 |u fzj |
| 700 | 1 | _ | |a Wouters, Dirk J. |0 P:(DE-HGF)0 |b 3 |
| 700 | 1 | _ | |a Menzel, Stephan |0 P:(DE-Juel1)158062 |b 4 |e Corresponding author |
| 773 | _ | _ | |a 10.1515/itit-2023-0018 |g Vol. 0, no. 0 |0 PERI:(DE-600)2028598-X |n 0 |p 1 |t Information technology |v 0 |y 2023 |x 0013-5720 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1007139/files/Invoice_APC600410706.pdf |
| 856 | 4 | _ | |y OpenAccess |u https://juser.fz-juelich.de/record/1007139/files/Bit-Slicing%20Approaches%20for%20Variability%20Aware%20ReRAM%20CIM%20Macros_final.pdf |
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