TY  - CONF
AU  - Vliex, Patrick
AU  - Bühler, Jonas
AU  - Cabrera Galicia, Alfonso Rafael
AU  - Schreckenberg, Lea
AU  - Otten, Rene
AU  - van Waasen, Stefan
TI  - Cryogenic CMOS for Local Qubit Control and Readout – A Path to Scaling
M1  - FZJ-2023-04442
PY  - 2023
AB  - The majority of the scientific research community for quantum computing agrees that an estimated number of around 106 qubits are required to build a universal quantum computer [1]. This number leads to foreseeable connectivity bottlenecks to feed all the required biasing, control and read-out signals into and out of the cryostat. A proposed solution is local cryogenic classical electronics, bringing control and read-out closer to the quantum bits themselves.For this task, the ZEA-2 – Electronic Systems institute – develops classical electronic systems using modern CMOS technologies, due to their low area footprint, ultra-low power consumption and natural synergy with semiconductor qubits. This poster highlights the ongoing development and measurement results at ZEA-2 for integrated cryogenic circuits and co-integrating them directly with qubits. This includes experimental results of a qubit bias voltage digital-to-analog converter (Bias-DAC) in a bulk 65 nm CMOS technology [2], placed at the milli-Kelvin stage alongside the qubit [3,4]. Results of cryogenic supply regulation circuits in an advanced 22nm FDSOI CMOS process are shown as well [5]. Furthermore, a brief introduction into CMOS and possible options for an optimized cryogenic specific CMOS technology is given to enhance future IC designs in power efficiency and outlook to qubit readout. This method of integration paves a way for QC scalability.[1] Vandersypen, L.M.K., Bluhm, H., Clarke, J.S. et al. Interfacing spin qubits in quantum dots and donors—hot, dense, and coherent. npj Quantum Inf 3, 34 (2017). https://doi.org/10.1038/s41534-017-0038-y[2] P. Vliex et al., "Bias Voltage DAC Operating at Cryogenic Temperatures for Solid-State Qubit Applications," in IEEE Solid-State Circuits Letters, vol. 3, pp. 218-221, 2020, doi: 10.1109/LSSC.2020.3011576.[3] R. Otten, L. Schreckenberg, P. Vliex et al., "Qubit Bias using a CMOS DAC at mK Temperatures," 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Glasgow, United Kingdom, 2022, pp. 1-4, doi: 10.1109/ICECS202256217.2022.9971043. [4] L. Schreckenberg, R. Otten, P. Vliex et al., "SiGe Qubit Biasing with a Cryogenic CMOS DAC at mK Temperature„ To be published in 2023 49th IEEE European Conference on Solid-State Circuits (ESSCIRC)[5] A. R. Cabrera-Galicia, A. Ashok, P. Vliex et al., "Towards the Development of Cryogenic Integrated Power Management Units," 2022 IEEE 15th Workshop on Low Temperature Electronics (WOLTE), Matera, Italy, 2022, pp. 1-4, doi: 10.1109/WOLTE55422.2022.9882781.
T2  - Silicon Quantum Electronics Workshop 2023
CY  - 31 Oct 2023 - 2 Nov 2023, Kyoto (Japan)
Y2  - 31 Oct 2023 - 2 Nov 2023
M2  - Kyoto, Japan
LB  - PUB:(DE-HGF)24
DO  - DOI:10.34734/FZJ-2023-04442
UR  - https://juser.fz-juelich.de/record/1017935
ER  -