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@INPROCEEDINGS{CabreraGalicia:1021124,
      author       = {Cabrera Galicia, Alfonso Rafael and Ashok, Arun and Vliex,
                      Patrick and Schreckenberg, Lea and Chava, Phanish and Baje
                      Shankarakrishna Bhat, Swasthik and Kruth, Andre and
                      Zambanini, Andre and van Waasen, Stefan},
      title        = {{P}ower {I}ntegrity {C}hallenges in {L}arge {S}cale
                      {Q}uantum {C}omputers and {S}olutions},
      school       = {Universität Duisburg-Essen},
      reportid     = {FZJ-2024-00578},
      year         = {2023},
      abstract     = {The ICs belonging to a quantum computer need stable and
                      regulated supply voltages for proper operation, e.g. the
                      phase noise of RF oscillators is dependent on their power
                      supply quality. Moreover, the power supply needs of a large
                      scale QC will be challenging to satisfy by simply using
                      supply lines connecting the ICs inside the cryostat with the
                      power sources at room temperature. This is because voltage
                      ripples (e.g. pulse tube vibration induced noise), ground
                      loops induced noise and dynamic load currents may affect the
                      ICs supply lines and compromise the QC power integrity.
                      Furthermore, it is expected that the connection lines
                      available in large scale QCs be scarce due to the limited
                      cryostat space. Therefore, the usage of several lines to set
                      different supply domains may not be possible and be a
                      restricting factor for the QCs scalability.This presentation
                      will address the cryogenic power integrity topic by
                      providing:— A review of the power integrity challenges
                      faced by cryogenic ICs. — Solution approaches focused on
                      the cryogenic setup and the use of cryogenic voltage
                      regulators. — Cryogenic characterization and modelling of
                      FDSOI technology (22 nm) for ICs design. — Design and test
                      of cryogenic voltage references, based on cryogenic Vth
                      saturation and Vth difference. — Design and test of a
                      cryogenic voltage regulator. — Design of Digital LDOs for
                      cryogenic applications. — An application case: cryogenic
                      voltage regulator applied to power the reference circuit of
                      a cryogenic DAC used for the DC voltage setting of a Single
                      Electron Transistor Quantum Dot},
      month         = {Oct},
      date          = {2023-10-24},
      organization  = {IEEE Workshop on Quantum Computing:
                       Devices, Cryogenic Electronics and
                       Packaging, Milpitas (USA), 24 Oct 2023
                       - 25 Oct 2023},
      subtyp        = {Invited},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5223 - Quantum-Computer Control Systems and Cryoelectronics
                      (POF4-522)},
      pid          = {G:(DE-HGF)POF4-5223},
      typ          = {PUB:(DE-HGF)31},
      doi          = {10.34734/FZJ-2024-00578},
      url          = {https://juser.fz-juelich.de/record/1021124},
}