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| Home > Publications database > High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain > print |
| 001 | 1021851 | ||
| 005 | 20240226075408.0 | ||
| 024 | 7 | _ | |a 10.23919/VLSITechnologyandCir57934.2023.10185373 |2 doi |
| 037 | _ | _ | |a FZJ-2024-01000 |
| 100 | 1 | _ | |a Han, Yi |0 P:(DE-Juel1)176845 |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |c Kyoto |d 2023-06-11 - 2023-06-16 |w Japan |
| 245 | _ | _ | |a High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain |
| 260 | _ | _ | |c 2023 |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a Other |2 DataCite |
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| 520 | _ | _ | |a The effect of band edge states is the critical issue for cryogenic CMOS, which worsens the performance of conventional MOSFETs at cryogenic temperature (Cryo-T) with saturated subthreshold swing (SS), large transition region (inflection phenomenon) and limited mobility. To address these problems, we fabricated gate-all-around (GAA) Si nanowire (NW) MOSFETs using fully silicided source/drain and dopant segregation. The effect of band edge states is significantly uppressed using this technology. Thus, SS, the effective average SSth and the transconductance (Gm) continuously improve as temperature decreases allowing us to achieve high performance NW FETs at 5.5 K with a record small SS of 2.3 mV/dec, ltra-small DIBL of 0.02 mV/V, and high Gm of 1.25mS/µm at Vd = 0.1 V. |
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| 700 | 1 | _ | |a Knoch, Joachim |0 P:(DE-HGF)0 |b 4 |
| 700 | 1 | _ | |a Zhao, Qing-Tai |0 P:(DE-Juel1)128649 |b 5 |u fzj |
| 773 | _ | _ | |a 10.23919/VLSITechnologyandCir57934.2023.10185373 |
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