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@ARTICLE{Knne:1023793,
      author       = {Künne, Matthias and Willmes, Alexander and Oberländer,
                      Max and Gorjaew, Christian and Teske, Julian D. and
                      Bhardwaj, Harsh and Beer, Max and Kammerloher, Eugen and
                      Otten, René and Seidler, Inga and Xue, Ran and Schreiber,
                      Lars R. and Bluhm, Hendrik},
      title        = {{T}he {S}pin{B}us {A}rchitecture: {S}caling {S}pin {Q}ubits
                      with {E}lectron {S}huttling},
      publisher    = {arXiv},
      reportid     = {FZJ-2024-01806},
      year         = {2023},
      abstract     = {Quantum processor architectures must enable scaling to
                      large qubit numbers while providing two-dimensional qubit
                      connectivity and exquisite operation fidelities. For
                      microwave-controlled semiconductor spin qubits, dense arrays
                      have made considerable progress, but are still limited in
                      size by wiring fan-out and exhibit significant crosstalk
                      between qubits. To overcome these limitations, we introduce
                      the SpinBus architecture, which uses electron shuttling to
                      connect qubits and features low operating frequencies and
                      enhanced qubit coherence. Device simulations for all
                      relevant operations in the Si/SiGe platform validate the
                      feasibility with established semiconductor patterning
                      technology and operation fidelities exceeding 99.9 $\%.$
                      Control using room temperature instruments can plausibly
                      support at least 144 qubits, but much larger numbers are
                      conceivable with cryogenic control circuits. Building on the
                      theoretical feasibility of high-fidelity spin-coherent
                      electron shuttling as key enabling factor, the SpinBus
                      architecture may be the basis for a spin-based quantum
                      processor that meets the scalability requirements for
                      practical quantum computing.},
      keywords     = {Quantum Physics (quant-ph) (Other) / Mesoscale and
                      Nanoscale Physics (cond-mat.mes-hall) (Other) / FOS:
                      Physical sciences (Other)},
      cin          = {PGI-11 / PGI-13},
      cid          = {I:(DE-Juel1)PGI-11-20170113 / I:(DE-Juel1)PGI-13-20210701},
      pnm          = {5221 - Advanced Solid-State Qubits and Qubit Systems
                      (POF4-522)},
      pid          = {G:(DE-HGF)POF4-5221},
      typ          = {PUB:(DE-HGF)25},
      doi          = {10.48550/ARXIV.2306.16348},
      url          = {https://juser.fz-juelich.de/record/1023793},
}