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@INPROCEEDINGS{Pedretti:1023855,
author = {Pedretti, G. and Böhm, F. and Hizzani, M. and
Bhattacharya, T. and Bruel, P. and Moon, J. and Serebryakov,
S. and Strukov, D. and Strachan, J. P. and Ignowski, J. and
Van Vaerenbergh, T. and Beausoleil, R. and Mohseni, M.},
title = {{Z}eroth and higher-order logic with content addressable
memories},
publisher = {IEEE},
reportid = {FZJ-2024-01857},
pages = {1-4},
year = {2023},
abstract = {Content Addressable Memories (CAMs) are attracting interest
as in-memory computational primitives, thanks to the
massively parallel search operation. Multiple flavors of
CAMs have been realized with nanoscale memory technology,
pushing their performance towards low power and latency. In
this work, we demonstrate how to use CAMs for asserting and
solving zeroth order and higher-order logic, in the form of
Boolean satisfiability (SAT) and satisfiability modulo
theories (SMT), respectively. We demonstrate a ~6.5× lower
area and ~4× lower energy per search compared with
state-of-the-art in-memory optimization problem solvers,
such as Hopfield Neural Network (HNN), with up to 175×
faster time-to-solution for problems with 150 variables.},
month = {Dec},
date = {2023-12-09},
organization = {2023 International Electron Devices
Meeting (IEDM), San Francisco (USA), 9
Dec 2023 - 13 Dec 2023},
cin = {PGI-14},
cid = {I:(DE-Juel1)PGI-14-20210412},
pnm = {5234 - Emerging NC Architectures (POF4-523)},
pid = {G:(DE-HGF)POF4-5234},
typ = {PUB:(DE-HGF)8},
doi = {10.1109/IEDM45741.2023.10413853},
url = {https://juser.fz-juelich.de/record/1023855},
}