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| 001 | 1023855 | ||
| 005 | 20250203103438.0 | ||
| 024 | 7 | _ | |a 10.1109/IEDM45741.2023.10413853 |2 doi |
| 037 | _ | _ | |a FZJ-2024-01857 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Pedretti, G. |0 P:(DE-HGF)0 |b 0 |
| 111 | 2 | _ | |a 2023 International Electron Devices Meeting (IEDM) |c San Francisco |d 2023-12-09 - 2023-12-13 |w USA |
| 245 | _ | _ | |a Zeroth and higher-order logic with content addressable memories |
| 260 | _ | _ | |c 2023 |b IEEE |
| 300 | _ | _ | |a 1-4 |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
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| 520 | _ | _ | |a Content Addressable Memories (CAMs) are attracting interest as in-memory computational primitives, thanks to the massively parallel search operation. Multiple flavors of CAMs have been realized with nanoscale memory technology, pushing their performance towards low power and latency. In this work, we demonstrate how to use CAMs for asserting and solving zeroth order and higher-order logic, in the form of Boolean satisfiability (SAT) and satisfiability modulo theories (SMT), respectively. We demonstrate a ~6.5× lower area and ~4× lower energy per search compared with state-of-the-art in-memory optimization problem solvers, such as Hopfield Neural Network (HNN), with up to 175× faster time-to-solution for problems with 150 variables. |
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| 700 | 1 | _ | |a Moon, J. |0 P:(DE-HGF)0 |b 5 |
| 700 | 1 | _ | |a Serebryakov, S. |0 P:(DE-HGF)0 |b 6 |
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| 700 | 1 | _ | |a Mohseni, M. |0 P:(DE-HGF)0 |b 12 |
| 773 | _ | _ | |a 10.1109/IEDM45741.2023.10413853 |
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