%0 Conference Paper
%A Schätzle, Fabian
%A Falquez, Carlos
%A Heinen, Stefan
%A Portero, Antoni
%A Suarez, Estela
%A Van Den Boom, Johannes
%A Van Waasen, Stefan
%A Ho, Nam
%T Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation
%I ACM New York, NY, USA
%M FZJ-2024-01918
%P 7
%D 2024
%< Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design - ACM New York, NY, USA, 2024. - ISBN 9798400717918 - doi:10.1145/3642921.3642956
%X The paper introduces a modeling methodology aimed at thoroughlyexploring the design space of multi-die chip architecture tailoredfor High-Performance Computing (HPC). For accurate simulations,we leverage the capabilities of gem5’s Ruby for its robust CPUmodels and cache coherence protocols, providing a comprehensiverepresentation of die architecture. Die-to-die interfaces are modeledusing SystemC TLM, offering flexibility to integrate with othersimulators. This enables co-simulation with varying abstractionlevels, making it well-suited for the design analysis of multi-diechip architecture.We present, to the best of our knowledge, the first attempt tointegrate gem5’s Ruby memory system with SystemC TLM for themodeling of multi-die chip architecture. The benefits of this modelare demonstrated through the instantiation of a multi-die designusing modern Arm architectures with four compute dies and twomemory dies. The multi-die chip’s functionality is validated byexecuting STREAM Triad with Linux, followed by a comparativeperformance analysis against a monolithic design.
%B RAPIDO '24: Rapid Simulation and Performance Evaluation for Design
%C 17 Jan 2024 - 19 Jan 2024, Munich Germany (Germany)
Y2 17 Jan 2024 - 19 Jan 2024
M2 Munich Germany, Germany
%F PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
%9 Contribution to a conference proceedingsContribution to a book
%U <Go to ISI:>//WOS:001179175100006
%R 10.1145/3642921.3642956
%U https://juser.fz-juelich.de/record/1024022