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@INPROCEEDINGS{Schtzle:1024022,
      author       = {Schätzle, Fabian and Falquez, Carlos and Heinen, Stefan
                      and Portero, Antoni and Suarez, Estela and Van Den Boom,
                      Johannes and Van Waasen, Stefan and Ho, Nam},
      title        = {{M}odeling methodology for multi-die chip design based on
                      gem5/{S}ystem{C} co-simulation},
      publisher    = {ACM New York, NY, USA},
      reportid     = {FZJ-2024-01918},
      pages        = {7},
      year         = {2024},
      comment      = {Proceedings of the 16th Workshop on Rapid Simulation and
                      Performance Evaluation for Design - ACM New York, NY, USA,
                      2024. - ISBN 9798400717918 - doi:10.1145/3642921.3642956},
      booktitle     = {Proceedings of the 16th Workshop on
                       Rapid Simulation and Performance
                       Evaluation for Design - ACM New York,
                       NY, USA, 2024. - ISBN 9798400717918 -
                       doi:10.1145/3642921.3642956},
      abstract     = {The paper introduces a modeling methodology aimed at
                      thoroughlyexploring the design space of multi-die chip
                      architecture tailoredfor High-Performance Computing (HPC).
                      For accurate simulations,we leverage the capabilities of
                      gem5’s Ruby for its robust CPUmodels and cache coherence
                      protocols, providing a comprehensiverepresentation of die
                      architecture. Die-to-die interfaces are modeledusing SystemC
                      TLM, offering flexibility to integrate with othersimulators.
                      This enables co-simulation with varying abstractionlevels,
                      making it well-suited for the design analysis of
                      multi-diechip architecture.We present, to the best of our
                      knowledge, the first attempt tointegrate gem5’s Ruby
                      memory system with SystemC TLM for themodeling of multi-die
                      chip architecture. The benefits of this modelare
                      demonstrated through the instantiation of a multi-die
                      designusing modern Arm architectures with four compute dies
                      and twomemory dies. The multi-die chip’s functionality is
                      validated byexecuting STREAM Triad with Linux, followed by a
                      comparativeperformance analysis against a monolithic
                      design.},
      month         = {Jan},
      date          = {2024-01-17},
      organization  = {RAPIDO '24: Rapid Simulation and
                       Performance Evaluation for Design,
                       Munich Germany (Germany), 17 Jan 2024 -
                       19 Jan 2024},
      cin          = {ZEA-2 / JSC},
      cid          = {I:(DE-Juel1)ZEA-2-20090406 / I:(DE-Juel1)JSC-20090406},
      pnm          = {5122 - Future Computing $\&$ Big Data Systems (POF4-512) /
                      5234 - Emerging NC Architectures (POF4-523) / EPI SGA2
                      (16ME0507K)},
      pid          = {G:(DE-HGF)POF4-5122 / G:(DE-HGF)POF4-5234 /
                      G:(BMBF)16ME0507K},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      UT           = {WOS:001179175100006},
      doi          = {10.1145/3642921.3642956},
      url          = {https://juser.fz-juelich.de/record/1024022},
}