| Home > Publications database > Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation > print |
| 001 | 1024022 | ||
| 005 | 20250129092348.0 | ||
| 024 | 7 | _ | |a 10.1145/3642921.3642956 |2 doi |
| 024 | 7 | _ | |a WOS:001179175100006 |2 WOS |
| 037 | _ | _ | |a FZJ-2024-01918 |
| 100 | 1 | _ | |a Schätzle, Fabian |0 P:(DE-Juel1)184395 |b 0 |e Corresponding author |
| 111 | 2 | _ | |a RAPIDO '24: Rapid Simulation and Performance Evaluation for Design |c Munich Germany |d 2024-01-17 - 2024-01-19 |w Germany |
| 245 | _ | _ | |a Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation |
| 260 | _ | _ | |c 2024 |b ACM New York, NY, USA |
| 295 | 1 | 0 | |a Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design - ACM New York, NY, USA, 2024. - ISBN 9798400717918 - doi:10.1145/3642921.3642956 |
| 300 | _ | _ | |a 7 |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
| 336 | 7 | _ | |a conferenceObject |2 DRIVER |
| 336 | 7 | _ | |a Output Types/Conference Paper |2 DataCite |
| 336 | 7 | _ | |a Contribution to a conference proceedings |b contrib |m contrib |0 PUB:(DE-HGF)8 |s 1710327372_3656 |2 PUB:(DE-HGF) |
| 336 | 7 | _ | |a Contribution to a book |0 PUB:(DE-HGF)7 |2 PUB:(DE-HGF) |m contb |
| 520 | _ | _ | |a The paper introduces a modeling methodology aimed at thoroughlyexploring the design space of multi-die chip architecture tailoredfor High-Performance Computing (HPC). For accurate simulations,we leverage the capabilities of gem5’s Ruby for its robust CPUmodels and cache coherence protocols, providing a comprehensiverepresentation of die architecture. Die-to-die interfaces are modeledusing SystemC TLM, offering flexibility to integrate with othersimulators. This enables co-simulation with varying abstractionlevels, making it well-suited for the design analysis of multi-diechip architecture.We present, to the best of our knowledge, the first attempt tointegrate gem5’s Ruby memory system with SystemC TLM for themodeling of multi-die chip architecture. The benefits of this modelare demonstrated through the instantiation of a multi-die designusing modern Arm architectures with four compute dies and twomemory dies. The multi-die chip’s functionality is validated byexecuting STREAM Triad with Linux, followed by a comparativeperformance analysis against a monolithic design. |
| 536 | _ | _ | |a 5122 - Future Computing & Big Data Systems (POF4-512) |0 G:(DE-HGF)POF4-5122 |c POF4-512 |f POF IV |x 0 |
| 536 | _ | _ | |a 5234 - Emerging NC Architectures (POF4-523) |0 G:(DE-HGF)POF4-5234 |c POF4-523 |f POF IV |x 1 |
| 536 | _ | _ | |a EPI SGA2 (16ME0507K) |0 G:(BMBF)16ME0507K |c 16ME0507K |x 2 |
| 588 | _ | _ | |a Dataset connected to CrossRef Conference |
| 700 | 1 | _ | |a Falquez, Carlos |0 P:(DE-Juel1)179531 |b 1 |
| 700 | 1 | _ | |a Heinen, Stefan |0 P:(DE-Juel1)180765 |b 2 |
| 700 | 1 | _ | |a Portero, Antoni |0 P:(DE-Juel1)177768 |b 3 |
| 700 | 1 | _ | |a Suarez, Estela |0 P:(DE-Juel1)142361 |b 4 |
| 700 | 1 | _ | |a Van Den Boom, Johannes |0 P:(DE-Juel1)162349 |b 5 |
| 700 | 1 | _ | |a Van Waasen, Stefan |0 P:(DE-Juel1)142562 |b 6 |
| 700 | 1 | _ | |a Ho, Nam |0 P:(DE-Juel1)176469 |b 7 |
| 773 | _ | _ | |a 10.1145/3642921.3642956 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1024022/files/Modeling_methodology_for_multi-die_chip_design_based_on_gem5SystemC_co-simulation.pdf |y Restricted |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1024022/files/Modeling_methodology_for_multi-die_chip_design_based_on_gem5SystemC_co-simulation.gif?subformat=icon |x icon |y Restricted |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1024022/files/Modeling_methodology_for_multi-die_chip_design_based_on_gem5SystemC_co-simulation.jpg?subformat=icon-1440 |x icon-1440 |y Restricted |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1024022/files/Modeling_methodology_for_multi-die_chip_design_based_on_gem5SystemC_co-simulation.jpg?subformat=icon-180 |x icon-180 |y Restricted |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1024022/files/Modeling_methodology_for_multi-die_chip_design_based_on_gem5SystemC_co-simulation.jpg?subformat=icon-640 |x icon-640 |y Restricted |
| 909 | C | O | |o oai:juser.fz-juelich.de:1024022 |p VDB |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 0 |6 P:(DE-Juel1)184395 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 1 |6 P:(DE-Juel1)179531 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 3 |6 P:(DE-Juel1)177768 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 4 |6 P:(DE-Juel1)142361 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 5 |6 P:(DE-Juel1)162349 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 6 |6 P:(DE-Juel1)142562 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 7 |6 P:(DE-Juel1)176469 |
| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Engineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action |1 G:(DE-HGF)POF4-510 |0 G:(DE-HGF)POF4-512 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Supercomputing & Big Data Infrastructures |9 G:(DE-HGF)POF4-5122 |x 0 |
| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Natural, Artificial and Cognitive Information Processing |1 G:(DE-HGF)POF4-520 |0 G:(DE-HGF)POF4-523 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Neuromorphic Computing and Network Dynamics |9 G:(DE-HGF)POF4-5234 |x 1 |
| 914 | 1 | _ | |y 2024 |
| 920 | _ | _ | |l yes |
| 920 | 1 | _ | |0 I:(DE-Juel1)ZEA-2-20090406 |k ZEA-2 |l Zentralinstitut für Elektronik |x 0 |
| 920 | 1 | _ | |0 I:(DE-Juel1)JSC-20090406 |k JSC |l Jülich Supercomputing Center |x 1 |
| 980 | _ | _ | |a contrib |
| 980 | _ | _ | |a VDB |
| 980 | _ | _ | |a contb |
| 980 | _ | _ | |a I:(DE-Juel1)ZEA-2-20090406 |
| 980 | _ | _ | |a I:(DE-Juel1)JSC-20090406 |
| 980 | _ | _ | |a UNRESTRICTED |
| 981 | _ | _ | |a I:(DE-Juel1)PGI-4-20110106 |
| Library | Collection | CLSMajor | CLSMinor | Language | Author |
|---|