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@INPROCEEDINGS{Yu:1024702,
      author       = {Yu, Zhenming and Yang, Ming-Jay and Finkbeiner, Jan and
                      Siegel, Sebastian and Strachan, John Paul and Neftci, Emre},
      title        = {{T}he {O}uroboros of {M}emristors: {N}eural {N}etworks
                      {F}acilitating {M}emristor {P}rogramming},
      publisher    = {FUNDACIO DE LA COMUNITAT VALENCIANA SCITO València},
      reportid     = {FZJ-2024-02369},
      pages        = {10},
      year         = {2023},
      comment      = {Proceedings of the Neuronics Conference - FUNDACIO DE LA
                      COMUNITAT VALENCIANA SCITO València, 2023. - ISBN -
                      doi:10.29363/nanoge.neuronics.2024.010},
      booktitle     = {Proceedings of the Neuronics
                       Conference - FUNDACIO DE LA COMUNITAT
                       VALENCIANA SCITO València, 2023. -
                       ISBN -
                       doi:10.29363/nanoge.neuronics.2024.010},
      abstract     = {Memristive devices hold promise to improve the scale and
                      efficiency of machine learning and neuromorphic hardware,
                      thanks to their compact size, low power consumption, and the
                      ability to perform matrix multiplications in constant time.
                      However, on-chip training with memristor arrays still faces
                      challenges, including device-to-device and cycle-to-cycle
                      variations, switching non-linearity, and especially SET and
                      RESET asymmetry [1], [2].To combat device non-linearity and
                      asymmetry, we propose to program memristors by harnessing
                      neural networks that map desired conductance updates to the
                      required pulse times. With our method, approximately $95\%$
                      of devices can be programmed within a relative percentage
                      difference of $±50\%$ from the target conductance after
                      just one attempt. Moreover, our neural pulse predictor
                      demonstrates a significant reduction in memristor
                      programming delay compared to traditional write-and-verify
                      methods, particularly advantageous in applications such as
                      on-chip training and fine-tuning.Upon deployment, the neural
                      pulse predictor can be integrated into memristor
                      accelerators, predicting pulses with an O(1) time complexity
                      while utilizing a minimal fraction of the available
                      memristor arrays, reducing hardware overhead compared with
                      previous works [3]-[6]. Additionally, multiple networks can
                      be trained to operate in parallel and enhance precision
                      across various conductance ranges.Our work contributes
                      significantly to the practical application of memristors,
                      particularly in reducing delays in memristor programming.
                      This work also offers a fresh perspective on the symbiotic
                      relationship between memristors and neural networks and sets
                      the stage for innovation in memristor optimizations.},
      month         = {Feb},
      date          = {2024-02-21},
      organization  = {Neuronics Conference, València
                       (Spain), 21 Feb 2024 - 23 Feb 2024},
      cin          = {PGI-14 / PGI-15},
      cid          = {I:(DE-Juel1)PGI-14-20210412 / I:(DE-Juel1)PGI-15-20210701},
      pnm          = {5233 - Memristive Materials and Devices (POF4-523)},
      pid          = {G:(DE-HGF)POF4-5233},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      doi          = {10.29363/nanoge.neuronics.2024.010},
      url          = {https://juser.fz-juelich.de/record/1024702},
}