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| Hauptseite > Publikationsdatenbank > The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming > print |
| Hauptseite > Publikationsdatenbank > The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming > print |
| 001 | 1024702 | ||
| 005 | 20250203103144.0 | ||
| 024 | 7 | _ | |a 10.29363/nanoge.neuronics.2024.010 |2 doi |
| 037 | _ | _ | |a FZJ-2024-02369 |
| 100 | 1 | _ | |a Yu, Zhenming |0 P:(DE-Juel1)190500 |b 0 |e Corresponding author |
| 111 | 2 | _ | |a Neuronics Conference |c València |d 2024-02-21 - 2024-02-23 |w Spain |
| 245 | _ | _ | |a The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming |
| 260 | _ | _ | |c 2023 |b FUNDACIO DE LA COMUNITAT VALENCIANA SCITO València |
| 295 | 1 | 0 | |a Proceedings of the Neuronics Conference - FUNDACIO DE LA COMUNITAT VALENCIANA SCITO València, 2023. - ISBN - doi:10.29363/nanoge.neuronics.2024.010 |
| 300 | _ | _ | |a 10 |
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| 336 | 7 | _ | |a Contribution to a book |0 PUB:(DE-HGF)7 |2 PUB:(DE-HGF) |m contb |
| 520 | _ | _ | |a Memristive devices hold promise to improve the scale and efficiency of machine learning and neuromorphic hardware, thanks to their compact size, low power consumption, and the ability to perform matrix multiplications in constant time. However, on-chip training with memristor arrays still faces challenges, including device-to-device and cycle-to-cycle variations, switching non-linearity, and especially SET and RESET asymmetry [1], [2].To combat device non-linearity and asymmetry, we propose to program memristors by harnessing neural networks that map desired conductance updates to the required pulse times. With our method, approximately 95% of devices can be programmed within a relative percentage difference of ±50% from the target conductance after just one attempt. Moreover, our neural pulse predictor demonstrates a significant reduction in memristor programming delay compared to traditional write-and-verify methods, particularly advantageous in applications such as on-chip training and fine-tuning.Upon deployment, the neural pulse predictor can be integrated into memristor accelerators, predicting pulses with an O(1) time complexity while utilizing a minimal fraction of the available memristor arrays, reducing hardware overhead compared with previous works [3]-[6]. Additionally, multiple networks can be trained to operate in parallel and enhance precision across various conductance ranges.Our work contributes significantly to the practical application of memristors, particularly in reducing delays in memristor programming. This work also offers a fresh perspective on the symbiotic relationship between memristors and neural networks and sets the stage for innovation in memristor optimizations. |
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| 773 | _ | _ | |a 10.29363/nanoge.neuronics.2024.010 |
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