001027983 001__ 1027983
001027983 005__ 20250129092506.0
001027983 037__ $$aFZJ-2024-04276
001027983 1001_ $$0P:(DE-Juel1)159350$$aGrewing, Christian$$b0$$eCorresponding author$$ufzj
001027983 1112_ $$aInternational Conference on Neuromorphic Coputing and Engineering$$cAachen$$d2024-06-03 - 2024-06-06$$gICNCE$$wGermany
001027983 245__ $$aInvention Disclosures relating to improved Signal Linearity and Signal to Noise Ratio enhancing Memristor Crossbar Capabilities
001027983 260__ $$c2024
001027983 3367_ $$033$$2EndNote$$aConference Paper
001027983 3367_ $$2DataCite$$aOther
001027983 3367_ $$2BibTeX$$aINPROCEEDINGS
001027983 3367_ $$2DRIVER$$aconferenceObject
001027983 3367_ $$2ORCID$$aLECTURE_SPEECH
001027983 3367_ $$0PUB:(DE-HGF)6$$2PUB:(DE-HGF)$$aConference Presentation$$bconf$$mconf$$s1719397807_25156$$xAfter Call
001027983 520__ $$aThe Von Neumann architecture, i.e. separation of memory and computation, results in large latency and energy consumption due to permanent read and write access to memory, known as the Von Neumann bottleneck. In contrast, biological brains feature colocation of computing and memory and are known to be very energy efficient. Therefore, enabling computing in memory seems a straightforward way to circumvent the bottleneck. Memristor based crossbar arrays have been proven to enable bio-inspired computing in memory [1]. To make use of the full capabilities of this concept the analog signal processing provided by the CMOS circuits is essential. Especially both, high signal linearity and signal to noise ratio (SNR) are most important. With an increased signal-to-noise margin, multilevel symbols can be used, expanding the possibilities of signal processing and enabling higher data bandwidth. However, the conversion of multilevel, analog or spike modulated information to classical CMOS may reduce the advantage of these concepts. For this reason, new concepts of energy efficient Network on Chip (NoC) designs, e.g. by utilizing analog symbols, must be developed.Within the BMBF funded project NEUROTEC II [2], special ICs are developed combining 28nm bulk CMOS circuits with memristive devices as a proof-of-principle of interacting bio-inspired crossbar based computing paradigms. For a later commercialization of the developed technology securing of the developed IP is required. In the ongoing development of the CMOS circuits three inventions have been disclosed so far (shortly described below), with three more to follow shortly.Folded cascode structure is used to ensure a maximum headroom in the circuits of the tiles and provide a low ohmic bias voltage. Parasitics in the control and supply lines can cause voltage drop and therefor mismatch in the operation points. A voltage regulation loop is used to provide a low ohmic bias voltage with a senseline, avoiding the offset through parasitic losses [3]. Building on this improvement a memristor crossbar array based analog signal conversion into multilevel symbols for easier use in an analog signal processing has been developed [4]. The NoC based concept of the chip interfacing multiple bio-inspired crossbar based computing paradigms could be further developed to improve every day applications such as location systems [5].[1]	A. Mehonic et al., Advanced Intelligent Systems, 2.11 (2020): 2000085[2]	https://www.neurotec.org/en, accessed 01.03.2024[3]	C. Grewing, Schaltkreis für ein Einstellen eines Memristors, European Patent Application, date of disclosure: 26.02.2024[4]	C. Grewing, Verfahren zur Wandlung eines analogen Signals, European Patent Application, date of disclosure: 21.12.2023[5]	C. Grewing, Anwendung einer neuromorph inspiererten hardware componente in einem Ortungssystem, European Patent Application, date of disclosure: 14.11.2023
001027983 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001027983 536__ $$0G:(DE-82)BMBF-16ME0398K$$aBMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)$$cBMBF-16ME0398K$$x1
001027983 7001_ $$0P:(DE-Juel1)133935$$aSchiek, Michael$$b1$$ufzj
001027983 7001_ $$0P:(DE-Juel1)176328$$aAshok, Arun$$b2$$ufzj
001027983 7001_ $$0P:(DE-Juel1)145837$$aZambanini, Andre$$b3$$ufzj
001027983 7001_ $$0P:(DE-Juel1)142562$$avan Waasen, Stefan$$b4$$ufzj
001027983 909CO $$ooai:juser.fz-juelich.de:1027983$$pVDB
001027983 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)159350$$aForschungszentrum Jülich$$b0$$kFZJ
001027983 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)133935$$aForschungszentrum Jülich$$b1$$kFZJ
001027983 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)176328$$aForschungszentrum Jülich$$b2$$kFZJ
001027983 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)145837$$aForschungszentrum Jülich$$b3$$kFZJ
001027983 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)142562$$aForschungszentrum Jülich$$b4$$kFZJ
001027983 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001027983 9141_ $$y2024
001027983 920__ $$lyes
001027983 9201_ $$0I:(DE-Juel1)ZEA-2-20090406$$kZEA-2$$lZentralinstitut für Elektronik$$x0
001027983 9201_ $$0I:(DE-Juel1)PGI-14-20210412$$kPGI-14$$lNeuromorphic Compute Nodes$$x1
001027983 980__ $$aconf
001027983 980__ $$aVDB
001027983 980__ $$aI:(DE-Juel1)ZEA-2-20090406
001027983 980__ $$aI:(DE-Juel1)PGI-14-20210412
001027983 980__ $$aUNRESTRICTED
001027983 981__ $$aI:(DE-Juel1)PGI-4-20110106