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@INPROCEEDINGS{Grewing:1027983,
      author       = {Grewing, Christian and Schiek, Michael and Ashok, Arun and
                      Zambanini, Andre and van Waasen, Stefan},
      title        = {{I}nvention {D}isclosures relating to improved {S}ignal
                      {L}inearity and {S}ignal to {N}oise {R}atio enhancing
                      {M}emristor {C}rossbar {C}apabilities},
      reportid     = {FZJ-2024-04276},
      year         = {2024},
      abstract     = {The Von Neumann architecture, i.e. separation of memory and
                      computation, results in large latency and energy consumption
                      due to permanent read and write access to memory, known as
                      the Von Neumann bottleneck. In contrast, biological brains
                      feature colocation of computing and memory and are known to
                      be very energy efficient. Therefore, enabling computing in
                      memory seems a straightforward way to circumvent the
                      bottleneck. Memristor based crossbar arrays have been proven
                      to enable bio-inspired computing in memory [1]. To make use
                      of the full capabilities of this concept the analog signal
                      processing provided by the CMOS circuits is essential.
                      Especially both, high signal linearity and signal to noise
                      ratio (SNR) are most important. With an increased
                      signal-to-noise margin, multilevel symbols can be used,
                      expanding the possibilities of signal processing and
                      enabling higher data bandwidth. However, the conversion of
                      multilevel, analog or spike modulated information to
                      classical CMOS may reduce the advantage of these concepts.
                      For this reason, new concepts of energy efficient Network on
                      Chip (NoC) designs, e.g. by utilizing analog symbols, must
                      be developed.Within the BMBF funded project NEUROTEC II [2],
                      special ICs are developed combining 28nm bulk CMOS circuits
                      with memristive devices as a proof-of-principle of
                      interacting bio-inspired crossbar based computing paradigms.
                      For a later commercialization of the developed technology
                      securing of the developed IP is required. In the ongoing
                      development of the CMOS circuits three inventions have been
                      disclosed so far (shortly described below), with three more
                      to follow shortly.Folded cascode structure is used to ensure
                      a maximum headroom in the circuits of the tiles and provide
                      a low ohmic bias voltage. Parasitics in the control and
                      supply lines can cause voltage drop and therefor mismatch in
                      the operation points. A voltage regulation loop is used to
                      provide a low ohmic bias voltage with a senseline, avoiding
                      the offset through parasitic losses [3]. Building on this
                      improvement a memristor crossbar array based analog signal
                      conversion into multilevel symbols for easier use in an
                      analog signal processing has been developed [4]. The NoC
                      based concept of the chip interfacing multiple bio-inspired
                      crossbar based computing paradigms could be further
                      developed to improve every day applications such as location
                      systems [5].[1] A. Mehonic et al., Advanced Intelligent
                      Systems, 2.11 (2020): 2000085[2]
                      https://www.neurotec.org/en, accessed 01.03.2024[3] C.
                      Grewing, Schaltkreis für ein Einstellen eines Memristors,
                      European Patent Application, date of disclosure:
                      26.02.2024[4] C. Grewing, Verfahren zur Wandlung eines
                      analogen Signals, European Patent Application, date of
                      disclosure: 21.12.2023[5] C. Grewing, Anwendung einer
                      neuromorph inspiererten hardware componente in einem
                      Ortungssystem, European Patent Application, date of
                      disclosure: 14.11.2023},
      month         = {Jun},
      date          = {2024-06-03},
      organization  = {International Conference on
                       Neuromorphic Coputing and Engineering,
                       Aachen (Germany), 3 Jun 2024 - 6 Jun
                       2024},
      subtyp        = {After Call},
      cin          = {ZEA-2 / PGI-14},
      cid          = {I:(DE-Juel1)ZEA-2-20090406 / I:(DE-Juel1)PGI-14-20210412},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF
                      16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://juser.fz-juelich.de/record/1027983},
}