TY  - CONF
AU  - Hizzani, Mohammad
AU  - Heittmann, Arne
AU  - Hutchinson, George
AU  - Dobrynin, Dmitri
AU  - Van Vaerenbergh, Thomas
AU  - Bhattacharya, Tinish
AU  - Renaudineau, Adrien
AU  - Strukov, Dmitri
AU  - Strachan, John Paul
TI  - Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines
PB  - IEEE
M1  - FZJ-2024-04779
SN  - 979-8-3503-3099-1
SP  - 1-5
PY  - 2024
AB  - Ising solvers offer a promising physics-based approach to tackle the challenging class of combinatorial optimization problems. However, typical solvers operate in a quadratic energy space, having only pair-wise coupling elements which already dominate area and energy. We show that such quadratization can cause severe problems: increased dimensionality, a rugged search landscape, and misalignment with the original objective function. Here, we design and quantify a higher-order Hopfield optimization solver, with 28nm CMOS technology and memristive couplings for lower area and energy computations. We combine algorithmic and circuit analysis to show quantitative advantages over quadratic Ising Machines (IM)s, yielding 48x and 72x reduction in time-to-solution (TTS) and energy-to-solution (ETS) respectively for Boolean satisfiability problems of 150 variables, with favorable scaling.
T2  - 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
CY  - 19 May 2024 - 22 May 2024, Singapore (Singapore)
Y2  - 19 May 2024 - 22 May 2024
M2  - Singapore, Singapore
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
UR  - <Go to ISI:>//WOS:001268541104029
DO  - DOI:10.1109/ISCAS58744.2024.10558658
UR  - https://juser.fz-juelich.de/record/1028722
ER  -