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| Hauptseite > Publikationsdatenbank > Heterogeneous Memory Aware Prefetching on High Performance Arm Processors > print |
| Hauptseite > Publikationsdatenbank > Heterogeneous Memory Aware Prefetching on High Performance Arm Processors > print |
| 001 | 1028952 | ||
| 005 | 20240722202104.0 | ||
| 024 | 7 | _ | |a 10.34734/FZJ-2024-04892 |2 datacite_doi |
| 037 | _ | _ | |a FZJ-2024-04892 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Saglam, Berk |0 P:(DE-Juel1)200201 |b 0 |e Corresponding author |u fzj |
| 245 | _ | _ | |a Heterogeneous Memory Aware Prefetching on High Performance Arm Processors |f - 2024-04-18 |
| 260 | _ | _ | |c 2024 |
| 300 | _ | _ | |a 142 |
| 336 | 7 | _ | |a Output Types/Supervised Student Publication |2 DataCite |
| 336 | 7 | _ | |a Thesis |0 2 |2 EndNote |
| 336 | 7 | _ | |a MASTERSTHESIS |2 BibTeX |
| 336 | 7 | _ | |a masterThesis |2 DRIVER |
| 336 | 7 | _ | |a Master Thesis |b master |m master |0 PUB:(DE-HGF)19 |s 1721622217_29528 |2 PUB:(DE-HGF) |
| 336 | 7 | _ | |a SUPERVISED_STUDENT_PUBLICATION |2 ORCID |
| 502 | _ | _ | |a Masterarbeit, Rheinische Friedrich-Wilhelms-Universität Bonn, 2024 |c Rheinische Friedrich-Wilhelms-Universität Bonn |b Masterarbeit |d 2024 |o 2024-04-18 |
| 520 | _ | _ | |a Modern computing often sees up to 80% of computation time spent on data retrieval,emphasizing the importance of prefetching for enhancing CPU data delivery speeds bymoving data from slower storage to faster caches. Balancing timeliness and aggressivenessis crucial for reducing access times. Utilizing heterogeneous memory, in this contextHBM2 and DDR5, serve different roles due to their bandwidth and capacity trade-offs, underscoring the need for balanced memory management and awareness whileprefetching.This work focuses on developing prefetching strategies for heterogeneous memoryconfigurations in high-performance Arm processors, targeting a system architecturecomprising 20 cores, with 16 cores dedicated to HBM2 and 4 cores dedicated to DDR5memory. The primary objective is to reduce latency and improve system performanceby introducing two innovative optimization strategies for prefetching. These strategiesmeticulously balance timeliness and aggressiveness by adaptively tuning the prefetchdegree and distance. These strategies adapt dynamically to the specific memory type andavailable bandwidth with consideration of the prefetch accuracy, optimizing prefetchingoperations for enhanced performance and efficiency. The Prefetcher are integrated withthe L2 cache and its performance is rigorously assessed through Gem5 simulations. Theseevaluations compare the effectiveness of adaptive optimization strategies for both Streamand PC-based Stride Prefetchers, utilizing the Arm Neoverse V1 as the computationalmodel.Findings reveal adaptive prefetching is boosting system performance, notably with HBM2and DDR5 Memory, while facing memory contention on DDR5. This research advancesprefetching strategies with the understanding of heterogeneous memory, advocatingfurther exploration to enhance high-performance computing efficiency and performance. |
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