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@PROCEEDINGS{Bende:1028978,
      author       = {Bende, Ankit and Singh, Simranjeet and Jha, Chandan Kumar
                      and Kempen, Tim and Cüppers, Felix and Bengel, Christopher
                      and Zambanini, Andre and Nielinger, Dennis and Patkar,
                      Sachin and Drechsler, Rolf and Waser, R. and Merchant,
                      Farhad and Rana, Vikas},
      title        = {{E}xperimental {V}alidation of {M}emristor-{A}ided {L}ogic
                      {U}sing 1{T}1{R} {T}a{O}x {RRAM} {C}rossbar {A}rray},
      publisher    = {arXiv},
      reportid     = {FZJ-2024-04910},
      year         = {2024},
      abstract     = {Memristor-aided logic (MAGIC) design style holds a high
                      promise for realizing digital logic-in-memory functionality.
                      The ability to implement a specific gate in a MAGIC design
                      style hinges on the SET-to-RESET threshold ratio. The TaOx
                      memristive devices exhibit distinct SET-to-RESET ratios,
                      enabling the implementation of OR and NOT operations. As the
                      adoption of the MAGIC design style gains momentum, it
                      becomes crucial to understand the breakdown of energy
                      consumption in the various phases of its operation. This
                      paper presents experimental demonstrations of the OR and NOT
                      gates on a 1T1R crossbar array. Additionally, it provides
                      insights into the energy distribution for performing these
                      operations at different stages. Through our experiments
                      across different gates, we found that the energy consumption
                      is dominated by initialization in the MAGIC design style.
                      The energy split-up is $14.8\%,$ $85\%,$ and $0.2\%$ for
                      execution, initialization, and read operations
                      respectively.},
      month         = {Jan},
      date          = {2024-01-06},
      organization  = {37th International Conference on VLSI
                       Design 2024, Kolkata (India), 6 Jan
                       2024 - 10 Jan 2024},
      keywords     = {Emerging Technologies (cs.ET) (Other) / FOS: Computer and
                      information sciences (Other)},
      cin          = {PGI-7 / JARA-FIT / PGI-10 / ZEA-2},
      cid          = {I:(DE-Juel1)PGI-7-20110106 / $I:(DE-82)080009_20140620$ /
                      I:(DE-Juel1)PGI-10-20170113 / I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF 16ME0399
                      - Verbundprojekt: Neuro-inspirierte Technologien der
                      künstlichen Intelligenz für die Elektronik der Zukunft -
                      NEUROTEC II - (BMBF-16ME0399) / BMBF 16ME0398K -
                      Verbundprojekt: Neuro-inspirierte Technologien der
                      künstlichen Intelligenz für die Elektronik der Zukunft -
                      NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0399 /
                      G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)26},
      doi          = {10.48550/ARXIV.2310.10460},
      url          = {https://juser.fz-juelich.de/record/1028978},
}