TY  - CONF
AU  - Chava, Phanish
AU  - Alius, Heidrun
AU  - Bühler, Jonas
AU  - Cabrera Galicia, Alfonso Rafael
AU  - Degenhardt, Carsten
AU  - Gneiting, Thomas
AU  - Harff, Markus
AU  - Heide, Thomas
AU  - Javorka, Peter
AU  - Lederer, Maximilain
AU  - Lehmann, Steffen
AU  - Simon, Maik
AU  - Su, Meng
AU  - Vliex, Patrick
AU  - van Waasen, Stefan
AU  - Witt, Christian
AU  - Zetzsche, Dennis
TI  - Evaluation of cryogenic models for FDSOI CMOS transistors
M1  - FZJ-2024-05369
PY  - 2024
AB  - Scalable quantum computers demand innovative solutions for tackling the wiring bottleneck to control an increasing number of qubits. Cryogenic electronics based on CMOS technologies are promising candidates which can operate down to deep-cryogenic temperatures and act as a communication and control interface to the quantum layer [1,2]. However, the performance of transistors used in these circuits is altered significantly when cooling from room temperature to cryogenic temperatures, which motivates accurate cryogenic modeling of transistors. We will report on cryogenic models tailored specifically for fully depleted silicon-on-insulator (FDSOI) transistors. We performed extensive DC characterization of transistors with subsequent modeling using the BSIM-IMG 102-9.6 model, which is the first version with a built-in cryogenic extension [3]. The preliminary models effectively represent the DC device behavior from 7 K up to room temperature. These models are used in industry standard EDA and simulation software, like Cadence Spectre. With the presented cryogenic models, we will show simulations at cryogenic temperatures. We will also compare the simulation results with the measured performance of a test chip in the temperature range from 7 K up to room temperature.
T2  - 16th IEEE Workshop on Low Temperature electronics
CY  - 3 Jun 2024 - 6 Jun 2024, Cagliari (Italy)
Y2  - 3 Jun 2024 - 6 Jun 2024
M2  - Cagliari, Italy
LB  - PUB:(DE-HGF)6
DO  - DOI:10.34734/FZJ-2024-05369
UR  - https://juser.fz-juelich.de/record/1030636
ER  -