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@INPROCEEDINGS{Chava:1030636,
      author       = {Chava, Phanish and Alius, Heidrun and Bühler, Jonas and
                      Cabrera Galicia, Alfonso Rafael and Degenhardt, Carsten and
                      Gneiting, Thomas and Harff, Markus and Heide, Thomas and
                      Javorka, Peter and Lederer, Maximilain and Lehmann, Steffen
                      and Simon, Maik and Su, Meng and Vliex, Patrick and van
                      Waasen, Stefan and Witt, Christian and Zetzsche, Dennis},
      title        = {{E}valuation of cryogenic models for {FDSOI} {CMOS}
                      transistors},
      reportid     = {FZJ-2024-05369},
      year         = {2024},
      abstract     = {Scalable quantum computers demand innovative solutions for
                      tackling the wiring bottleneck to control an increasing
                      number of qubits. Cryogenic electronics based on CMOS
                      technologies are promising candidates which can operate down
                      to deep-cryogenic temperatures and act as a communication
                      and control interface to the quantum layer [1,2]. However,
                      the performance of transistors used in these circuits is
                      altered significantly when cooling from room temperature to
                      cryogenic temperatures, which motivates accurate cryogenic
                      modeling of transistors. We will report on cryogenic models
                      tailored specifically for fully depleted
                      silicon-on-insulator (FDSOI) transistors. We performed
                      extensive DC characterization of transistors with subsequent
                      modeling using the BSIM-IMG 102-9.6 model, which is the
                      first version with a built-in cryogenic extension [3]. The
                      preliminary models effectively represent the DC device
                      behavior from 7 K up to room temperature. These models are
                      used in industry standard EDA and simulation software, like
                      Cadence Spectre. With the presented cryogenic models, we
                      will show simulations at cryogenic temperatures. We will
                      also compare the simulation results with the measured
                      performance of a test chip in the temperature range from 7 K
                      up to room temperature.},
      month         = {Jun},
      date          = {2024-06-03},
      organization  = {16th IEEE Workshop on Low Temperature
                       electronics, Cagliari (Italy), 3 Jun
                       2024 - 6 Jun 2024},
      subtyp        = {Other},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5223 - Quantum-Computer Control Systems and Cryoelectronics
                      (POF4-522)},
      pid          = {G:(DE-HGF)POF4-5223},
      typ          = {PUB:(DE-HGF)6},
      doi          = {10.34734/FZJ-2024-05369},
      url          = {https://juser.fz-juelich.de/record/1030636},
}