001031162 001__ 1031162
001031162 005__ 20250116215106.0
001031162 0247_ $$2datacite_doi$$a10.34734/FZJ-2024-05566
001031162 0247_ $$2doi$$a10.1145/3695794.3695800
001031162 037__ $$aFZJ-2024-05566
001031162 041__ $$aEnglish
001031162 1001_ $$0P:(DE-Juel1)200201$$aSaglam, Berk$$b0$$eCorresponding author$$ufzj
001031162 245__ $$aData Prefetching on Processors with Heterogeneous Memory
001031162 260__ $$c2024
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001031162 520__ $$aHeterogeneous memory architectures, such as a mix of High Bandwidth Memory (HBM) and Double Data Rate (DDR), offer flexible performance optimization by leveraging the high bandwidth of HBM along with the high capacity of DDR. However, these architectures present challenges in balancing bandwidth and capacity to maximize overall system performance and complicate hardware design.In a flat memory organization mixing HBM and DDR, prefetchers must carefully reduce prefetch requests on DDR when transitioning from HBM to avoid performance degradation due to potential bandwidth saturation. Traditional hardware prefetchers, which typically assume a homogeneous memory, are unaware of this circumstance, so they may not be effective in heterogeneous memory architectures. The paper enhances the aggressiveness of prefetchers in this kind of architecture. Our technique enables a prefetcher to dynamically determine the optimal prefetch degree and distance based on memory type. It balances prefetch aggressiveness and timeliness through an adaptive strategy informed by bandwidth utilization and prefetch metrics learned for each memory type. We evaluated the technique within the Stride and Stream Prefetchers at L2 in a gem5 model of a 20-core Arm Neoverse V1-like architecture, a mix of HBM2 and DDR5. The simulation results, focusing on scientific benchmarks, showed that the technique effectively guides prefetchers to near-optimal static configurations. On HBM2, the adaptation strategy detects bandwidth availability and prefetches more aggressively to boost performance, achieving speedups of $1.3\times$ to $2.3\times$. On DDR5, when faced with saturated bandwidth contention, the adaptation strategy switches to conservative prefetching mode to mitigate performance degradation.
001031162 536__ $$0G:(DE-HGF)POF4-5122$$a5122 - Future Computing & Big Data Systems (POF4-512)$$cPOF4-512$$fPOF IV$$x0
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001031162 7001_ $$0P:(DE-Juel1)176469$$aHo, Nam$$b1$$eCorresponding author$$ufzj
001031162 7001_ $$0P:(DE-Juel1)179531$$aFalquez, Carlos$$b2$$ufzj
001031162 7001_ $$0P:(DE-Juel1)177768$$aPortero, Antonio$$b3$$ufzj
001031162 7001_ $$0P:(DE-Juel1)184395$$aSchätzle, Fabian$$b4$$ufzj
001031162 7001_ $$0P:(DE-Juel1)142361$$aSuarez, Estela$$b5$$ufzj
001031162 7001_ $$0P:(DE-HGF)0$$aPleiter, Dirk$$b6
001031162 773__ $$a10.1145/3695794.3695800$$t10th International Symposium on Memory Systems (MEMSY24)$$y2024
001031162 8564_ $$uhttps://juser.fz-juelich.de/record/1031162/files/Hybrid_Memory_Prefetching.pdf$$yOpenAccess
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001031162 9101_ $$0I:(DE-HGF)0$$6P:(DE-HGF)0$$a Division of Computational Science and Technology, EECS, KTH Royal Institute of Technology$$b6
001031162 9131_ $$0G:(DE-HGF)POF4-512$$1G:(DE-HGF)POF4-510$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5122$$aDE-HGF$$bKey Technologies$$lEngineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action$$vSupercomputing & Big Data Infrastructures$$x0
001031162 9141_ $$y2024
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