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| 001 | 1031162 | ||
| 005 | 20250116215106.0 | ||
| 024 | 7 | _ | |a 10.34734/FZJ-2024-05566 |2 datacite_doi |
| 024 | 7 | _ | |a 10.1145/3695794.3695800 |2 doi |
| 037 | _ | _ | |a FZJ-2024-05566 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Saglam, Berk |0 P:(DE-Juel1)200201 |b 0 |e Corresponding author |u fzj |
| 245 | _ | _ | |a Data Prefetching on Processors with Heterogeneous Memory |
| 260 | _ | _ | |c 2024 |
| 336 | 7 | _ | |a Preprint |b preprint |m preprint |0 PUB:(DE-HGF)25 |s 1737022946_7816 |2 PUB:(DE-HGF) |
| 336 | 7 | _ | |a WORKING_PAPER |2 ORCID |
| 336 | 7 | _ | |a Electronic Article |0 28 |2 EndNote |
| 336 | 7 | _ | |a preprint |2 DRIVER |
| 336 | 7 | _ | |a ARTICLE |2 BibTeX |
| 336 | 7 | _ | |a Output Types/Working Paper |2 DataCite |
| 520 | _ | _ | |a Heterogeneous memory architectures, such as a mix of High Bandwidth Memory (HBM) and Double Data Rate (DDR), offer flexible performance optimization by leveraging the high bandwidth of HBM along with the high capacity of DDR. However, these architectures present challenges in balancing bandwidth and capacity to maximize overall system performance and complicate hardware design.In a flat memory organization mixing HBM and DDR, prefetchers must carefully reduce prefetch requests on DDR when transitioning from HBM to avoid performance degradation due to potential bandwidth saturation. Traditional hardware prefetchers, which typically assume a homogeneous memory, are unaware of this circumstance, so they may not be effective in heterogeneous memory architectures. The paper enhances the aggressiveness of prefetchers in this kind of architecture. Our technique enables a prefetcher to dynamically determine the optimal prefetch degree and distance based on memory type. It balances prefetch aggressiveness and timeliness through an adaptive strategy informed by bandwidth utilization and prefetch metrics learned for each memory type. We evaluated the technique within the Stride and Stream Prefetchers at L2 in a gem5 model of a 20-core Arm Neoverse V1-like architecture, a mix of HBM2 and DDR5. The simulation results, focusing on scientific benchmarks, showed that the technique effectively guides prefetchers to near-optimal static configurations. On HBM2, the adaptation strategy detects bandwidth availability and prefetches more aggressively to boost performance, achieving speedups of $1.3\times$ to $2.3\times$. On DDR5, when faced with saturated bandwidth contention, the adaptation strategy switches to conservative prefetching mode to mitigate performance degradation. |
| 536 | _ | _ | |a 5122 - Future Computing & Big Data Systems (POF4-512) |0 G:(DE-HGF)POF4-5122 |c POF4-512 |f POF IV |x 0 |
| 536 | _ | _ | |a EPI SGA2 (16ME0507K) |0 G:(BMBF)16ME0507K |c 16ME0507K |x 1 |
| 700 | 1 | _ | |a Ho, Nam |0 P:(DE-Juel1)176469 |b 1 |e Corresponding author |u fzj |
| 700 | 1 | _ | |a Falquez, Carlos |0 P:(DE-Juel1)179531 |b 2 |u fzj |
| 700 | 1 | _ | |a Portero, Antonio |0 P:(DE-Juel1)177768 |b 3 |u fzj |
| 700 | 1 | _ | |a Schätzle, Fabian |0 P:(DE-Juel1)184395 |b 4 |u fzj |
| 700 | 1 | _ | |a Suarez, Estela |0 P:(DE-Juel1)142361 |b 5 |u fzj |
| 700 | 1 | _ | |a Pleiter, Dirk |0 P:(DE-HGF)0 |b 6 |
| 773 | _ | _ | |a 10.1145/3695794.3695800 |y 2024 |t 10th International Symposium on Memory Systems (MEMSY24) |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1031162/files/Hybrid_Memory_Prefetching.pdf |y OpenAccess |
| 909 | C | O | |o oai:juser.fz-juelich.de:1031162 |p openaire |p open_access |p VDB |p driver |p dnbdelivery |
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| 910 | 1 | _ | |a Division of Computational Science and Technology, EECS, KTH Royal Institute of Technology |0 I:(DE-HGF)0 |b 6 |6 P:(DE-HGF)0 |
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| 914 | 1 | _ | |y 2024 |
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