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@INPROCEEDINGS{Shamookh:1031258,
      author       = {Shamookh, Muhammad and Ashok, Arun and Zambanini, Andre and
                      Geläschus, Anton Ulrich and Grewing, Christian and Bahr,
                      Andreas and van Waasen, Stefan},
      title        = {3.35{V} {H}igh {V}oltage {E}lectroforming {G}enerator in
                      28nm with 5.3m{V} ripple and $46\%$ efficiency for {H}f{O}2
                      based {M}emristors},
      reportid     = {FZJ-2024-05636},
      year         = {2024},
      abstract     = {A high voltage (HV) that is usually not available in modern
                      nodes is required to form memristors. A scalable
                      implementation requires the HV to be generated on chip and
                      this work proposes such a generator. In a 28nm CMOS process,
                      a three-stage charge pump (CP) is designed in the absence of
                      HV-transistors. For the HfO2 based memristor electroforming
                      (EF), a developed CP runs with an efficiency of $46.5\%$ at
                      an output voltage of 3.35V and a load current of 184.9μA
                      from a 1.8V supply. The optimum design strategy for a
                      cross-coupled charge pump (CC-CP) is explained for a low
                      ripple < 6mV, while at the same time ensuring lower
                      capacitor value and high reliability. The results of an
                      over-voltage analytical investigation have important
                      ramifications for lowering the overall area without
                      compromising output voltage or CP efficiency. Monte Carlo
                      simulation for 200 samples were also performed to verify the
                      design’s robustness. However, the proposed design can be
                      readily extended to any memristor application or material,
                      thereby paving the way for the integration of fully
                      integrated chips (ICs) for memristor EF in smaller
                      technology nodes.},
      month         = {Jul},
      date          = {2024-07-02},
      organization  = {International Conference on Synthesis,
                       Modeling, Analysis and Simulation
                       Methods, and Application to Circuit
                       Design, Volos (Greece), 2 Jul 2024 - 5
                       Jul 2024},
      subtyp        = {After Call},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF
                      16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://juser.fz-juelich.de/record/1031258},
}