Home > Publications database > 3.35V High Voltage Electroforming Generator in 28nm with 5.3mV ripple and 46% efficiency for HfO2 based Memristors > print

001     1031258
005     20250129092503.0
037 _ _ |a FZJ-2024-05636
041 _ _ |a English
100 1 _ |a Shamookh, Muhammad
|0 P:(DE-Juel1)201575
|b 0
111 2 _ |a International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Application to Circuit Design
|g SMACD 2024
|c Volos
|d 2024-07-02 - 2024-07-05
|w Greece
245 _ _ |a 3.35V High Voltage Electroforming Generator in 28nm with 5.3mV ripple and 46% efficiency for HfO2 based Memristors
260 _ _ |c 2024
336 7 _ |a Conference Paper
|0 33
|2 EndNote
336 7 _ |a Other
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336 7 _ |a INPROCEEDINGS
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336 7 _ |a LECTURE_SPEECH
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336 7 _ |a Conference Presentation
|b conf
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|s 1733819084_14572
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|x After Call
520 _ _ |a A high voltage (HV) that is usually not available in modern nodes is required to form memristors. A scalable implementation requires the HV to be generated on chip and this work proposes such a generator. In a 28nm CMOS process, a three-stage charge pump (CP) is designed in the absence of HV-transistors. For the HfO2 based memristor electroforming (EF), a developed CP runs with an efficiency of 46.5% at an output voltage of 3.35V and a load current of 184.9μA from a 1.8V supply. The optimum design strategy for a cross-coupled charge pump (CC-CP) is explained for a low ripple < 6mV, while at the same time ensuring lower capacitor value and high reliability. The results of an over-voltage analytical investigation have important ramifications for lowering the overall area without compromising output voltage or CP efficiency. Monte Carlo simulation for 200 samples were also performed to verify the design’s robustness. However, the proposed design can be readily extended to any memristor application or material, thereby paving the way for the integration of fully integrated chips (ICs) for memristor EF in smaller technology nodes.
536 _ _ |a 5234 - Emerging NC Architectures (POF4-523)
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536 _ _ |a BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)
|0 G:(DE-82)BMBF-16ME0398K
|c BMBF-16ME0398K
|x 1
650 1 7 |a Engineering, Industrial Materials and Processing
|0 V:(DE-MLZ)GC-1601-2016
|2 V:(DE-HGF)
|x 0
700 1 _ |a Ashok, Arun
|0 P:(DE-Juel1)176328
|b 1
700 1 _ |a Zambanini, Andre
|0 P:(DE-Juel1)145837
|b 2
700 1 _ |a Geläschus, Anton Ulrich
|0 P:(DE-HGF)0
|b 3
700 1 _ |a Grewing, Christian
|0 P:(DE-Juel1)159350
|b 4
700 1 _ |a Bahr, Andreas
|0 P:(DE-HGF)0
|b 5
700 1 _ |a van Waasen, Stefan
|0 P:(DE-Juel1)142562
|b 6
909 C O |p VDB
|o oai:juser.fz-juelich.de:1031258
910 1 _ |a Forschungszentrum Jülich
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910 1 _ |a Forschungszentrum Jülich
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913 1 _ |a DE-HGF
|b Key Technologies
|l Natural, Artificial and Cognitive Information Processing
|1 G:(DE-HGF)POF4-520
|0 G:(DE-HGF)POF4-523
|3 G:(DE-HGF)POF4
|2 G:(DE-HGF)POF4-500
|4 G:(DE-HGF)POF
|v Neuromorphic Computing and Network Dynamics
|9 G:(DE-HGF)POF4-5234
|x 0
914 1 _ |y 2024
920 _ _ |l yes
920 1 _ |0 I:(DE-Juel1)ZEA-2-20090406
|k ZEA-2
|l Zentralinstitut für Elektronik
|x 0
980 _ _ |a conf
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980 _ _ |a I:(DE-Juel1)ZEA-2-20090406
980 _ _ |a UNRESTRICTED
981 _ _ |a I:(DE-Juel1)PGI-4-20110106

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