001031654 001__ 1031654
001031654 005__ 20250129092507.0
001031654 037__ $$aFZJ-2024-05770
001031654 041__ $$aEnglish
001031654 1001_ $$0P:(DE-Juel1)201575$$aShamookh, Muhammad$$b0
001031654 245__ $$aIntegrated High Voltage Generator for Memristor Electroforming$$f2023-10-16 - 2024-04-15
001031654 260__ $$c2024
001031654 300__ $$a74
001031654 3367_ $$2DataCite$$aOutput Types/Supervised Student Publication
001031654 3367_ $$02$$2EndNote$$aThesis
001031654 3367_ $$2BibTeX$$aMASTERSTHESIS
001031654 3367_ $$2DRIVER$$amasterThesis
001031654 3367_ $$0PUB:(DE-HGF)19$$2PUB:(DE-HGF)$$aMaster Thesis$$bmaster$$mmaster$$s1733819158_5474
001031654 3367_ $$2ORCID$$aSUPERVISED_STUDENT_PUBLICATION
001031654 502__ $$aMasterarbeit, Hamburg University of Technology (TUHH), 2024$$bMasterarbeit$$cHamburg University of Technology (TUHH)$$d2024$$o2024-09-24
001031654 520__ $$aFor state-of-the-art computing needs, such as machine learning (ML),compute-in-memory (CIM) architectures are evolving as a good choice com-pared to traditional von-Neumann architecture. CIM processors use cross-bars to process within memory for performing multiply and accumulate op-erations in ML algorithms. Memristors which are essentially non-volatileprogrammable resistors are forefront as memory elements in the cross-barsdue to their scalability and energy-efficient feature. The memristor has to gothrough the process of electroforming (EF) for an application.The process of EF a memristor involves setting the low resistance state(LRS) via current compliance Icc. This EF phase varies in duration basedon the EF voltage VEF, requiring high voltage (HV) as a trade-off withEF time. To achieve CMOS-memristor scalable co-integration, on-chip HVgeneration is essential. A voltage that is usually not available in modernnodes is required to form HfO2 based memristors and this work proposes sucha generator. In a 28 nm CMOS process, a three-stage charge pump (CP) isdesigned without using HV-transistors. For the HfO2 based memristor EF,a developed CP runs with an efficiency of 46.5% at an output voltage of 3.35V and a load current of 184.9 μA from a 1.8 V supply.The study further explains an analytical design approach for a proposedthree-stage CP, focusing on achieving optimal balance among efficiency, out-put ripple, current compliance Icc, and minimal capacitance. The resultsof an over-voltage analytical investigation have important ramifications forlowering the overall area without compromising output voltage or CP ef-ficiency. Corners and Monte Carlo simulations are conducted to validatethe robustness of the design. By eliminating HV-transistors or multi-phaseclocks, the design effectively reduces system costs, enhancing the efficiencyand scalability of emerging neuromorphic systems.Finally, with the developed CP, a EF system is proposed for the 64 × 64memristor cross-bar array with considerations for power consumption, IR-drop, and settling time. The proposed architecture requires the need foradvanced drivers, known as gate drivers or column drivers. The drivers areanalyzed and understood at a block level, followed by a deeper investigationinto the individual components. Subsequently, these insights are synthesizedto develop a comprehensive memristor EF system architecture. The futurework will focus on verifying and testing the functionality of the system ar-chitecture along with the driver chip to ensure its effectiveness in practicalapplications.The proposed system design can be readily extended to any memristorapplication or material, thereby paving the way for the integration of fullyintegrated chips (ICs) for memristor EF in smaller technology nodes.
001031654 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001031654 536__ $$0G:(DE-82)BMBF-16ME0398K$$aBMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)$$cBMBF-16ME0398K$$x1
001031654 65017 $$0V:(DE-MLZ)GC-1601-2016$$2V:(DE-HGF)$$aEngineering, Industrial Materials and Processing$$x0
001031654 7001_ $$0P:(DE-Juel1)176328$$aAshok, Arun$$b1$$eThesis advisor
001031654 7001_ $$0P:(DE-HGF)0$$aGaläschus, Anton Ulrich$$b2$$eThesis advisor
001031654 909CO $$ooai:juser.fz-juelich.de:1031654$$pVDB
001031654 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)201575$$aForschungszentrum Jülich$$b0$$kFZJ
001031654 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)176328$$aForschungszentrum Jülich$$b1$$kFZJ
001031654 9101_ $$0I:(DE-HGF)0$$6P:(DE-HGF)0$$a Hamburg University of Technology$$b2
001031654 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001031654 9141_ $$y2024
001031654 9201_ $$0I:(DE-Juel1)ZEA-2-20090406$$kZEA-2$$lZentralinstitut für Elektronik$$x0
001031654 980__ $$amaster
001031654 980__ $$aVDB
001031654 980__ $$aI:(DE-Juel1)ZEA-2-20090406
001031654 980__ $$aUNRESTRICTED
001031654 981__ $$aI:(DE-Juel1)PGI-4-20110106