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@MASTERSTHESIS{Shamookh:1031654,
      author       = {Shamookh, Muhammad},
      othercontributors = {Ashok, Arun and Galäschus, Anton Ulrich},
      title        = {{I}ntegrated {H}igh {V}oltage {G}enerator for {M}emristor
                      {E}lectroforming},
      school       = {Hamburg University of Technology (TUHH)},
      type         = {Masterarbeit},
      reportid     = {FZJ-2024-05770},
      pages        = {74},
      year         = {2024},
      note         = {Masterarbeit, Hamburg University of Technology (TUHH),
                      2024},
      abstract     = {For state-of-the-art computing needs, such as machine
                      learning (ML),compute-in-memory (CIM) architectures are
                      evolving as a good choice com-pared to traditional
                      von-Neumann architecture. CIM processors use cross-bars to
                      process within memory for performing multiply and accumulate
                      op-erations in ML algorithms. Memristors which are
                      essentially non-volatileprogrammable resistors are forefront
                      as memory elements in the cross-barsdue to their scalability
                      and energy-efficient feature. The memristor has to gothrough
                      the process of electroforming (EF) for an application.The
                      process of EF a memristor involves setting the low
                      resistance state(LRS) via current compliance Icc. This EF
                      phase varies in duration basedon the EF voltage VEF,
                      requiring high voltage (HV) as a trade-off withEF time. To
                      achieve CMOS-memristor scalable co-integration, on-chip
                      HVgeneration is essential. A voltage that is usually not
                      available in modernnodes is required to form HfO2 based
                      memristors and this work proposes sucha generator. In a 28
                      nm CMOS process, a three-stage charge pump (CP) isdesigned
                      without using HV-transistors. For the HfO2 based memristor
                      EF,a developed CP runs with an efficiency of $46.5\%$ at an
                      output voltage of 3.35V and a load current of 184.9 μA from
                      a 1.8 V supply.The study further explains an analytical
                      design approach for a proposedthree-stage CP, focusing on
                      achieving optimal balance among efficiency, out-put ripple,
                      current compliance Icc, and minimal capacitance. The
                      resultsof an over-voltage analytical investigation have
                      important ramifications forlowering the overall area without
                      compromising output voltage or CP ef-ficiency. Corners and
                      Monte Carlo simulations are conducted to validatethe
                      robustness of the design. By eliminating HV-transistors or
                      multi-phaseclocks, the design effectively reduces system
                      costs, enhancing the efficiencyand scalability of emerging
                      neuromorphic systems.Finally, with the developed CP, a EF
                      system is proposed for the 64 × 64memristor cross-bar array
                      with considerations for power consumption, IR-drop, and
                      settling time. The proposed architecture requires the need
                      foradvanced drivers, known as gate drivers or column
                      drivers. The drivers areanalyzed and understood at a block
                      level, followed by a deeper investigationinto the individual
                      components. Subsequently, these insights are synthesizedto
                      develop a comprehensive memristor EF system architecture.
                      The futurework will focus on verifying and testing the
                      functionality of the system ar-chitecture along with the
                      driver chip to ensure its effectiveness in
                      practicalapplications.The proposed system design can be
                      readily extended to any memristorapplication or material,
                      thereby paving the way for the integration of
                      fullyintegrated chips (ICs) for memristor EF in smaller
                      technology nodes.},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF
                      16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)19},
      url          = {https://juser.fz-juelich.de/record/1031654},
}