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@ARTICLE{Renner:1032331,
      author       = {Renner, Alpha and Sheldon, Forrest and Zlotnik, Anatoly and
                      Tao, Louis and Sornborger, Andrew},
      title        = {{T}he backpropagation algorithm implemented on spiking
                      neuromorphic hardware},
      journal      = {Nature Communications},
      volume       = {15},
      number       = {1},
      issn         = {2041-1723},
      address      = {[London]},
      publisher    = {Nature Publishing Group UK},
      reportid     = {FZJ-2024-06157},
      pages        = {9691},
      year         = {2024},
      abstract     = {The capabilities of natural neural systems have inspired
                      both new generations of machine learning algorithms as well
                      as neuromorphic, very large-scale integrated circuits
                      capable of fast, low-power information processing. However,
                      it has been argued that most modern machine learning
                      algorithms are not neurophysiologically plausible. In
                      particular, the workhorse of modern deep learning, the
                      backpropagation algorithm, has proven difficult to translate
                      to neuromorphic hardware. This study presents a
                      neuromorphic, spiking backpropagation algorithm based on
                      synfire-gated dynamical information coordination and
                      processing implemented on Intel’s Loihi neuromorphic
                      research processor. We demonstrate a proof-of-principle
                      three-layer circuit that learns to classify digits and
                      clothing items from the MNIST and Fashion MNIST datasets. To
                      our knowledge, this is the first work to show a Spiking
                      Neural Network implementation of the exact backpropagation
                      algorithm that is fully on-chip without a computer in the
                      loop. It is competitive in accuracy with off-chip trained
                      SNNs and achieves an energy-delay product suitable for edge
                      computing. This implementation shows a path for using
                      in-memory, massively parallel neuromorphic processors for
                      low-power, low-latency implementation of modern deep
                      learning applications.},
      cin          = {PGI-15},
      ddc          = {500},
      cid          = {I:(DE-Juel1)PGI-15-20210701},
      pnm          = {5234 - Emerging NC Architectures (POF4-523)},
      pid          = {G:(DE-HGF)POF4-5234},
      typ          = {PUB:(DE-HGF)16},
      pubmed       = {39516210},
      UT           = {WOS:001352395400002},
      doi          = {10.1038/s41467-024-53827-9},
      url          = {https://juser.fz-juelich.de/record/1032331},
}