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001033659 020__ $$a10.1145/3589737.3605967
001033659 037__ $$aFZJ-2024-06531
001033659 041__ $$aEnglish
001033659 1001_ $$0P:(DE-Juel1)188273$$aNeftci, Emre$$b0$$ufzj
001033659 1112_ $$aICONS 2023$$cSanta Fe$$d2023-08-01 - 2023-08-03$$wMexico
001033659 245__ $$aInterfacing Neuromorphic Hardware with Machine Learning Frameworks - A Review
001033659 260__ $$aNew York$$bAssociation for Computing Machinery$$c2023
001033659 29510 $$aICONS '23: Proceedings of the 2023 International Conference on Neuromorphic Systems
001033659 300__ $$a1-8
001033659 3367_ $$2ORCID$$aCONFERENCE_PAPER
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001033659 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1732775589_8303
001033659 3367_ $$0PUB:(DE-HGF)7$$2PUB:(DE-HGF)$$aContribution to a book$$mcontb
001033659 520__ $$aWith the emergence of neuromorphic hardware as a promising low-power parallel computing platform, the need for tools that allow researchers and engineers to efficiently interact with such hardware is rapidly growing. Machine learning frameworks like Tensorflow, PyTorch and JAX have been instrumental for the success of machine learning in recent years as they enable seamless interaction with traditional machine learning accelerators such as GPUs and TPUs. In stark contrast, interfacing with neuromorphic hardware remains difficult since the aforementioned frameworks do not address the challenges associated with mapping neural network models and algorithms to physical hardware. In this paper, we review the various strategies employed throughout the neuromorphic computing community to tackle these challenges and categorize them according to their methodologies and implementation effort. This classification serves as a guideline for device engineers and software developers alike to enable them to choose the best-fit solution in regard of their demands and available resources. Finally, we provide a JAX-based proof-of-concept implementation of a compilation pipeline tailored to the needs of researchers in the early stages of device development, where parts of the computational graph can be mapped onto custom hardware via operations exposed through a C++ or Python interface. The code is available at https://github.com/PGI15/xbarax.
001033659 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001033659 7001_ $$0P:(DE-Juel1)192147$$aLohoff, Jamie$$b1$$ufzj
001033659 7001_ $$0P:(DE-Juel1)190500$$aYu, Zhenming$$b2$$ufzj
001033659 7001_ $$0P:(DE-Juel1)190112$$aFinkbeiner, Jan Robert$$b3$$ufzj
001033659 7001_ $$0P:(DE-Juel1)204426$$aKaya, Anil$$b4$$ufzj
001033659 7001_ $$0P:(DE-Juel1)195754$$aStewart, Kenneth$$b5
001033659 7001_ $$0P:(DE-HGF)0$$aLui, Hin Wai$$b6
001033659 773__ $$p270/ Article No. 16
001033659 909CO $$ooai:juser.fz-juelich.de:1033659$$pVDB
001033659 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)188273$$aForschungszentrum Jülich$$b0$$kFZJ
001033659 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)192147$$aForschungszentrum Jülich$$b1$$kFZJ
001033659 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)190500$$aForschungszentrum Jülich$$b2$$kFZJ
001033659 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)190112$$aForschungszentrum Jülich$$b3$$kFZJ
001033659 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)204426$$aForschungszentrum Jülich$$b4$$kFZJ
001033659 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001033659 9141_ $$y2024
001033659 9201_ $$0I:(DE-Juel1)PGI-15-20210701$$kPGI-15$$lNeuromorphic Software Eco System$$x0
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