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@INPROCEEDINGS{Kuriakose:1033840,
      author       = {Kuriakose, Neethu and Ashok, Arun and Kusuma, Sabitha and
                      Grewing, Christian and Zambanini, Andre and van Waasen,
                      Stefan and Kruth, Andre},
      title        = {{I}ntegrated {M}emristor {C}ontrol and {C}rossbar {A}rray
                      {D}esign using {TSMC} 28 nm {T}echnology},
      school       = {University of Duisburg Essen},
      reportid     = {FZJ-2024-06681},
      year         = {2024},
      abstract     = {The crossbar array architecture with memristors is used for
                      vector matrix multiplication (VMM) and acts askernels in
                      neuromorphic computing [1]. A conductance control scheme
                      with a regulated voltage source willimprove the architecture
                      and reduce the possible potential divider effects due to
                      line resistances [2]. A change inconductance is also
                      possible with the provision of a regulated current source
                      and measuring the voltage acrossthe memristor. A regulated
                      2T1R memristor conductance control architecture is proposed
                      in this work, whichavoids the potential divider effect and
                      virtual ground scenario in a regular crossbar scheme, as
                      well as conductancecontrol by passing a regulated current
                      through memristors as shown in Fig. 1. The sneak path
                      current is notallowed to enter by providing the ground
                      potential to both terminals of memristors. The control
                      architecture witha 2×2 array size is successfully taped out
                      in a 28 nm CMOS technology. The MEMCTRL block includes a
                      corecorresponding to the intended conductance control
                      architecture, incorporating voltage mode control and
                      currentmode control in two rows, core biasing circuits,
                      resistive DAC, and a digital control block for the pulse
                      widthgenerator with chip layout shown in Fig. 2. The pulse
                      width control and digital configurations for selecting
                      rowsand columns are done with an integrated RISC-V
                      processor, running with a clock frequency of up to 100
                      MHz.Alternatively, direct access is enabled through a JTAG
                      programming interface. The readout circuit is
                      implementedwith a current source SAR ADC. The overall size
                      of the chip is 1.4 mm by 1.0 mm, of which the memristor
                      controlcircuit incorporates an area of 0.4 mm by 0.5 mm. The
                      memristors are not co-integrated in this
                      architecture,however, pins are provided for accessing
                      external memristors.},
      month         = {Nov},
      date          = {2024-11-10},
      organization  = {MEMRISYS 2024, Seoul (South Korea), 10
                       Nov 2024 - 13 Nov 2024},
      subtyp        = {After Call},
      cin          = {ZEA-2 / PGI-4},
      cid          = {I:(DE-Juel1)ZEA-2-20090406 / I:(DE-Juel1)PGI-4-20110106},
      pnm          = {5234 - Emerging NC Architectures (POF4-523)},
      pid          = {G:(DE-HGF)POF4-5234},
      typ          = {PUB:(DE-HGF)6},
      doi          = {10.34734/FZJ-2024-06681},
      url          = {https://juser.fz-juelich.de/record/1033840},
}