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| 001 | 1033840 | ||
| 005 | 20250624202310.0 | ||
| 024 | 7 | _ | |a 10.34734/FZJ-2024-06681 |2 datacite_doi |
| 037 | _ | _ | |a FZJ-2024-06681 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Kuriakose, Neethu |0 P:(DE-Juel1)188691 |b 0 |u fzj |
| 111 | 2 | _ | |a MEMRISYS 2024 |c Seoul |d 2024-11-10 - 2024-11-13 |w South Korea |
| 245 | _ | _ | |a Integrated Memristor Control and Crossbar Array Design using TSMC 28 nm Technology |
| 260 | _ | _ | |c 2024 |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a Other |2 DataCite |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
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| 502 | _ | _ | |c University of Duisburg Essen |
| 520 | _ | _ | |a The crossbar array architecture with memristors is used for vector matrix multiplication (VMM) and acts askernels in neuromorphic computing [1]. A conductance control scheme with a regulated voltage source willimprove the architecture and reduce the possible potential divider effects due to line resistances [2]. A change inconductance is also possible with the provision of a regulated current source and measuring the voltage acrossthe memristor. A regulated 2T1R memristor conductance control architecture is proposed in this work, whichavoids the potential divider effect and virtual ground scenario in a regular crossbar scheme, as well as conductancecontrol by passing a regulated current through memristors as shown in Fig. 1. The sneak path current is notallowed to enter by providing the ground potential to both terminals of memristors. The control architecture witha 2×2 array size is successfully taped out in a 28 nm CMOS technology. The MEMCTRL block includes a corecorresponding to the intended conductance control architecture, incorporating voltage mode control and currentmode control in two rows, core biasing circuits, resistive DAC, and a digital control block for the pulse widthgenerator with chip layout shown in Fig. 2. The pulse width control and digital configurations for selecting rowsand columns are done with an integrated RISC-V processor, running with a clock frequency of up to 100 MHz.Alternatively, direct access is enabled through a JTAG programming interface. The readout circuit is implementedwith a current source SAR ADC. The overall size of the chip is 1.4 mm by 1.0 mm, of which the memristor controlcircuit incorporates an area of 0.4 mm by 0.5 mm. The memristors are not co-integrated in this architecture,however, pins are provided for accessing external memristors. |
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| 700 | 1 | _ | |a Ashok, Arun |0 P:(DE-Juel1)176328 |b 1 |u fzj |
| 700 | 1 | _ | |a Kusuma, Sabitha |0 P:(DE-Juel1)187432 |b 2 |u fzj |
| 700 | 1 | _ | |a Grewing, Christian |0 P:(DE-Juel1)159350 |b 3 |u fzj |
| 700 | 1 | _ | |a Zambanini, Andre |0 P:(DE-Juel1)145837 |b 4 |u fzj |
| 700 | 1 | _ | |a van Waasen, Stefan |0 P:(DE-Juel1)142562 |b 5 |u fzj |
| 700 | 1 | _ | |a Kruth, Andre |0 P:(DE-Juel1)156521 |b 6 |u fzj |
| 856 | 4 | _ | |u https://www.memrisys2024.org/ |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1033840/files/MEMRISYS_2024_Integrated%20Memristor%20Control%20and%20Crossbar%20Array%20Design%20using%20TSMC%2028%20nm%20Technology.pdf |y OpenAccess |
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