001033974 001__ 1033974
001033974 005__ 20250129092414.0
001033974 0247_ $$2datacite_doi$$a10.34734/FZJ-2024-06810
001033974 037__ $$aFZJ-2024-06810
001033974 041__ $$aEnglish
001033974 1001_ $$0P:(DE-Juel1)203161$$aZhao, Wei$$b0$$ufzj
001033974 1112_ $$a31st IEEE International Conference on Electronics Circuits and Systems$$cNancy$$d2024-11-18 - 2024-11-20$$gICECS'24$$wFrance
001033974 245__ $$aOn-Chip Advanced Control Algorithm for Memristor Operations with Integrated RISC-V Core
001033974 260__ $$c2024
001033974 3367_ $$033$$2EndNote$$aConference Paper
001033974 3367_ $$2DataCite$$aOther
001033974 3367_ $$2BibTeX$$aINPROCEEDINGS
001033974 3367_ $$2DRIVER$$aconferenceObject
001033974 3367_ $$2ORCID$$aLECTURE_SPEECH
001033974 3367_ $$0PUB:(DE-HGF)6$$2PUB:(DE-HGF)$$aConference Presentation$$bconf$$mconf$$s1733815182_7466$$xAfter Call
001033974 520__ $$aAdvancements in memory technology havepositioned memristors at the forefront of non-volatile memoryapplications, necessitating precise control mechanisms toaccurately program memristor cells to their respective states.This study delves into the utilization of a RISC-V processor andPWM generators to configure registers for analog conductancecontrol of crossbar memristor array architecture for accuratevoltage and current mode operations. The core contribution isthe development of a flexible and efficient control algorithmspecifically designed for RISC-V. A Universal VerificationMethodology Framework (UVMF) testbench is employedto validate control signals, ensuring their accuracy priorto hardware implementation. Results indicate significantenhancements in control efficiency, underlining the potential forintegrating RISC-V with memristor technology.
001033974 536__ $$0G:(DE-82)BMBF-16ME0398K$$aBMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)$$cBMBF-16ME0398K$$x0
001033974 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x1
001033974 65027 $$0V:(DE-MLZ)SciArea-250$$2V:(DE-HGF)$$aOthers$$x0
001033974 65017 $$0V:(DE-MLZ)GC-1601-2016$$2V:(DE-HGF)$$aEngineering, Industrial Materials and Processing$$x0
001033974 7001_ $$0P:(DE-Juel1)188691$$aKuriakose, Neethu$$b1$$ufzj
001033974 7001_ $$0P:(DE-Juel1)187432$$aKusuma, Sabitha$$b2$$ufzj
001033974 7001_ $$0P:(DE-Juel1)177867$$aAmmari, Abdelaziz$$b3$$ufzj
001033974 7001_ $$0P:(DE-Juel1)176328$$aAshok, Arun$$b4$$ufzj
001033974 7001_ $$0P:(DE-Juel1)159350$$aGrewing, Christian$$b5$$ufzj
001033974 7001_ $$0P:(DE-Juel1)145837$$aZambanini, Andre$$b6$$ufzj
001033974 7001_ $$0P:(DE-Juel1)142562$$avan Waasen, Stefan$$b7$$ufzj
001033974 8564_ $$uhttps://juser.fz-juelich.de/record/1033974/files/On-Chip%20Advanced%20Control%20Algorithm%20for%20Memristor%20Operations%20with%20Integrated%20RISC-V%20Core.pdf$$yOpenAccess
001033974 909CO $$ooai:juser.fz-juelich.de:1033974$$pdriver$$pVDB$$popen_access$$popenaire
001033974 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)203161$$aForschungszentrum Jülich$$b0$$kFZJ
001033974 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)188691$$aForschungszentrum Jülich$$b1$$kFZJ
001033974 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)187432$$aForschungszentrum Jülich$$b2$$kFZJ
001033974 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)177867$$aForschungszentrum Jülich$$b3$$kFZJ
001033974 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)176328$$aForschungszentrum Jülich$$b4$$kFZJ
001033974 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)159350$$aForschungszentrum Jülich$$b5$$kFZJ
001033974 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)145837$$aForschungszentrum Jülich$$b6$$kFZJ
001033974 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)142562$$aForschungszentrum Jülich$$b7$$kFZJ
001033974 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001033974 9141_ $$y2024
001033974 915__ $$0StatID:(DE-HGF)0510$$2StatID$$aOpenAccess
001033974 920__ $$lyes
001033974 9201_ $$0I:(DE-Juel1)ZEA-2-20090406$$kZEA-2$$lZentralinstitut für Elektronik$$x0
001033974 9801_ $$aFullTexts
001033974 980__ $$aconf
001033974 980__ $$aVDB
001033974 980__ $$aUNRESTRICTED
001033974 980__ $$aI:(DE-Juel1)ZEA-2-20090406
001033974 981__ $$aI:(DE-Juel1)PGI-4-20110106