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@INPROCEEDINGS{Zhao:1033974,
      author       = {Zhao, Wei and Kuriakose, Neethu and Kusuma, Sabitha and
                      Ammari, Abdelaziz and Ashok, Arun and Grewing, Christian and
                      Zambanini, Andre and van Waasen, Stefan},
      title        = {{O}n-{C}hip {A}dvanced {C}ontrol {A}lgorithm for
                      {M}emristor {O}perations with {I}ntegrated {RISC}-{V}
                      {C}ore},
      reportid     = {FZJ-2024-06810},
      year         = {2024},
      abstract     = {Advancements in memory technology havepositioned memristors
                      at the forefront of non-volatile memoryapplications,
                      necessitating precise control mechanisms toaccurately
                      program memristor cells to their respective states.This
                      study delves into the utilization of a RISC-V processor
                      andPWM generators to configure registers for analog
                      conductancecontrol of crossbar memristor array architecture
                      for accuratevoltage and current mode operations. The core
                      contribution isthe development of a flexible and efficient
                      control algorithmspecifically designed for RISC-V. A
                      Universal VerificationMethodology Framework (UVMF) testbench
                      is employedto validate control signals, ensuring their
                      accuracy priorto hardware implementation. Results indicate
                      significantenhancements in control efficiency, underlining
                      the potential forintegrating RISC-V with memristor
                      technology.},
      month         = {Nov},
      date          = {2024-11-18},
      organization  = {31st IEEE International Conference on
                       Electronics Circuits and Systems, Nancy
                       (France), 18 Nov 2024 - 20 Nov 2024},
      subtyp        = {After Call},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte
                      Technologien der künstlichen Intelligenz für die
                      Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K) /
                      5234 - Emerging NC Architectures (POF4-523)},
      pid          = {G:(DE-82)BMBF-16ME0398K / G:(DE-HGF)POF4-5234},
      typ          = {PUB:(DE-HGF)6},
      doi          = {10.34734/FZJ-2024-06810},
      url          = {https://juser.fz-juelich.de/record/1033974},
}