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Poster (Other) FZJ-2024-07075
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Architecting Fast and Energy-Efficient Hardware Accelerators for Emerging ML Workloads Using Hardware-Software Co-Design



2024

PhD Forum, 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, IncheonIncheon, South Korea, 22 Jan 2024 - 25 Jan 20242024-01-222024-01-25

Contributing Institute(s):
  1. JARA Institut Green IT (PGI-10)
Research Program(s):
  1. 5234 - Emerging NC Architectures (POF4-523) (POF4-523)
  2. BMBF 16ME0399 - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0399) (BMBF-16ME0399)
  3. BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K) (BMBF-16ME0398K)

Appears in the scientific report 2024
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Document types > Presentations > Poster
Institute Collections > PGI > PGI-10
Workflow collections > Public records
Publications database
 Record created 2024-12-13, last modified 2025-01-21
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