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| Hauptseite > Publikationsdatenbank > Porting Lattice QCD benchmark to upcoming STX stencil/tensor accelerator > print |
| Hauptseite > Publikationsdatenbank > Porting Lattice QCD benchmark to upcoming STX stencil/tensor accelerator > print |
| 001 | 1037866 | ||
| 005 | 20250203103253.0 | ||
| 037 | _ | _ | |a FZJ-2025-01009 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Schlepphorst, Simon |0 P:(DE-Juel1)198707 |b 0 |e Corresponding author |
| 111 | 2 | _ | |a 41st Lattice Conference |g Lattice 2024 |c Liverpool |d 2024-07-28 - 2024-08-03 |w UK |
| 245 | _ | _ | |a Porting Lattice QCD benchmark to upcoming STX stencil/tensor accelerator |
| 260 | _ | _ | |c 2024 |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a Other |2 DataCite |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
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| 520 | _ | _ | |a Developed under the European Processor Initiative (EPI) the STX stencil/tensor accelerator aims to achieve a 5-10x higher energy efficiency over general purpose compute units. The architecture consists of specialised MIMD compute units which are supported and controlled by RISC-V cores. We describe a co-design effort between hardware, software, and application development focused around porting a LQCD benchmark to this new architecture. |
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| 700 | 1 | _ | |a Krieg, Stefan |0 P:(DE-Juel1)132171 |b 1 |
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| 914 | 1 | _ | |y 2024 |
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