001038031 001__ 1038031
001038031 005__ 20250207080353.0
001038031 0247_ $$2doi$$a10.1109/AICAS59952.2024.10595913
001038031 0247_ $$2WOS$$aWOS:001280469200057
001038031 037__ $$aFZJ-2025-01080
001038031 1001_ $$0P:(DE-Juel1)190500$$aYu, Zhenming$$b0$$ufzj
001038031 1112_ $$a2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)$$cAbu Dhabi$$d2024-04-22 - 2024-04-25$$wUnited Arab Emirates
001038031 245__ $$aThe Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming
001038031 260__ $$aAbu Dhabi$$bIEEE$$c2024
001038031 29510 $$a2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS) : [Proceedings] - IEEE, 2024. - ISBN 979-8-3503-8363-8 - doi:10.1109/AICAS59952.2024.10595913
001038031 300__ $$a398-402
001038031 3367_ $$2ORCID$$aCONFERENCE_PAPER
001038031 3367_ $$033$$2EndNote$$aConference Paper
001038031 3367_ $$2BibTeX$$aINPROCEEDINGS
001038031 3367_ $$2DRIVER$$aconferenceObject
001038031 3367_ $$2DataCite$$aOutput Types/Conference Paper
001038031 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1738911779_10583
001038031 3367_ $$0PUB:(DE-HGF)7$$2PUB:(DE-HGF)$$aContribution to a book$$mcontb
001038031 4900_ $$aInternational Conference on AI Circuits and Systems (AICAS)
001038031 520__ $$aMemristive devices hold promise to improve the scale and efficiency of machine learning and neuromorphic hardware, thanks to their compact size, low power consumption, and the ability to perform matrix multiplications in constant time. However, on-chip training with memristor arrays still faces challenges, including device-to-device and cycle-to-cycle variations, switching non-linearity, and especially SET and RESET asymmetry [1], [2]. To combat device non-linearity and asymmetry, we propose to program memristors by harnessing neural networks that map desired conductance updates to the required pulse times. With our method, approximately 95% of devices can be programmed within a relative percentage difference of ±50% from the target conductance after just one attempt. Our approach substantially reduces memristor programming delays compared to traditional write-and-verify methods, presenting an advantageous solution for on-chip training scenarios. Furthermore, our proposed neural network can be accelerated by memristor arrays upon deployment, providing assistance while reducing hardware overhead compared with previous works [3]–[6].This work contributes significantly to the practical application of memristors, particularly in reducing delays in memristor programming. It also envisions the future development of memristor-based machine learning accelerators.
001038031 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001038031 536__ $$0G:(BMBF)16ME0400$$aBMBF 16ME0400 - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (16ME0400)$$c16ME0400$$x1
001038031 536__ $$0G:(BMBF)03ZU1106CA$$aBMBF 03ZU1106CA - NeuroSys: Algorithm-Hardware Co-Design (Projekt C) - A (03ZU1106CA)$$c03ZU1106CA$$x2
001038031 536__ $$0G:(DE-Juel1)BMBF-03ZU1106CB$$aBMBF 03ZU1106CB - NeuroSys: Algorithm-Hardware Co-Design (Projekt C) - B (BMBF-03ZU1106CB)$$cBMBF-03ZU1106CB$$x3
001038031 536__ $$0G:(DE-HGF)POF4-5233$$a5233 - Memristive Materials and Devices (POF4-523)$$cPOF4-523$$fPOF IV$$x4
001038031 588__ $$aDataset connected to CrossRef Conference
001038031 7001_ $$0P:(DE-Juel1)192385$$aYang, Ming-Jay$$b1$$ufzj
001038031 7001_ $$0P:(DE-Juel1)190112$$aFinkbeiner, Jan$$b2$$ufzj
001038031 7001_ $$0P:(DE-Juel1)174486$$aSiegel, Sebastian$$b3$$ufzj
001038031 7001_ $$0P:(DE-Juel1)188145$$aStrachan, John Paul$$b4$$ufzj
001038031 7001_ $$0P:(DE-Juel1)188273$$aNeftci, Emre$$b5$$eCorresponding author
001038031 773__ $$a10.1109/AICAS59952.2024.10595913
001038031 8564_ $$uhttps://ieeexplore.ieee.org/document/10595913
001038031 8564_ $$uhttps://juser.fz-juelich.de/record/1038031/files/The_Ouroboros_of_Memristors_Neural_Networks_Facilitating_Memristor_Programming.pdf$$yRestricted
001038031 909CO $$ooai:juser.fz-juelich.de:1038031$$pVDB
001038031 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)190500$$aForschungszentrum Jülich$$b0$$kFZJ
001038031 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)192385$$aForschungszentrum Jülich$$b1$$kFZJ
001038031 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)190112$$aForschungszentrum Jülich$$b2$$kFZJ
001038031 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)174486$$aForschungszentrum Jülich$$b3$$kFZJ
001038031 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)188145$$aForschungszentrum Jülich$$b4$$kFZJ
001038031 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)188273$$aForschungszentrum Jülich$$b5$$kFZJ
001038031 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001038031 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5233$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x1
001038031 9141_ $$y2024
001038031 920__ $$lyes
001038031 9201_ $$0I:(DE-Juel1)PGI-15-20210701$$kPGI-15$$lNeuromorphic Software Eco System$$x0
001038031 9201_ $$0I:(DE-Juel1)PGI-14-20210412$$kPGI-14$$lNeuromorphic Compute Nodes$$x1
001038031 980__ $$acontrib
001038031 980__ $$aVDB
001038031 980__ $$acontb
001038031 980__ $$aI:(DE-Juel1)PGI-15-20210701
001038031 980__ $$aI:(DE-Juel1)PGI-14-20210412
001038031 980__ $$aUNRESTRICTED