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@INPROCEEDINGS{Yu:1038031,
      author       = {Yu, Zhenming and Yang, Ming-Jay and Finkbeiner, Jan and
                      Siegel, Sebastian and Strachan, John Paul and Neftci, Emre},
      title        = {{T}he {O}uroboros of {M}emristors: {N}eural {N}etworks
                      {F}acilitating {M}emristor {P}rogramming},
      address      = {Abu Dhabi},
      publisher    = {IEEE},
      reportid     = {FZJ-2025-01080},
      series       = {International Conference on AI Circuits and Systems
                      (AICAS)},
      pages        = {398-402},
      year         = {2024},
      comment      = {2024 IEEE 6th International Conference on AI Circuits and
                      Systems (AICAS) : [Proceedings] - IEEE, 2024. - ISBN
                      979-8-3503-8363-8 - doi:10.1109/AICAS59952.2024.10595913},
      booktitle     = {2024 IEEE 6th International Conference
                       on AI Circuits and Systems (AICAS) :
                       [Proceedings] - IEEE, 2024. - ISBN
                       979-8-3503-8363-8 -
                       doi:10.1109/AICAS59952.2024.10595913},
      abstract     = {Memristive devices hold promise to improve the scale and
                      efficiency of machine learning and neuromorphic hardware,
                      thanks to their compact size, low power consumption, and the
                      ability to perform matrix multiplications in constant time.
                      However, on-chip training with memristor arrays still faces
                      challenges, including device-to-device and cycle-to-cycle
                      variations, switching non-linearity, and especially SET and
                      RESET asymmetry [1], [2]. To combat device non-linearity and
                      asymmetry, we propose to program memristors by harnessing
                      neural networks that map desired conductance updates to the
                      required pulse times. With our method, approximately $95\%$
                      of devices can be programmed within a relative percentage
                      difference of $±50\%$ from the target conductance after
                      just one attempt. Our approach substantially reduces
                      memristor programming delays compared to traditional
                      write-and-verify methods, presenting an advantageous
                      solution for on-chip training scenarios. Furthermore, our
                      proposed neural network can be accelerated by memristor
                      arrays upon deployment, providing assistance while reducing
                      hardware overhead compared with previous works
                      [3]–[6].This work contributes significantly to the
                      practical application of memristors, particularly in
                      reducing delays in memristor programming. It also envisions
                      the future development of memristor-based machine learning
                      accelerators.},
      month         = {Apr},
      date          = {2024-04-22},
      organization  = {2024 IEEE 6th International Conference
                       on AI Circuits and Systems (AICAS), Abu
                       Dhabi (United Arab Emirates), 22 Apr
                       2024 - 25 Apr 2024},
      cin          = {PGI-15 / PGI-14},
      cid          = {I:(DE-Juel1)PGI-15-20210701 / I:(DE-Juel1)PGI-14-20210412},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF 16ME0400
                      - Verbundprojekt: Neuro-inspirierte Technologien der
                      künstlichen Intelligenz für die Elektronik der Zukunft -
                      NEUROTEC II - (16ME0400) / BMBF 03ZU1106CA - NeuroSys:
                      Algorithm-Hardware Co-Design (Projekt C) - A (03ZU1106CA) /
                      BMBF 03ZU1106CB - NeuroSys: Algorithm-Hardware Co-Design
                      (Projekt C) - B (BMBF-03ZU1106CB) / 5233 - Memristive
                      Materials and Devices (POF4-523)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(BMBF)16ME0400 / G:(BMBF)03ZU1106CA
                      / G:(DE-Juel1)BMBF-03ZU1106CB / G:(DE-HGF)POF4-5233},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      UT           = {WOS:001280469200057},
      doi          = {10.1109/AICAS59952.2024.10595913},
      url          = {https://juser.fz-juelich.de/record/1038031},
}