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@ARTICLE{Yu:1038036,
      author       = {Yu, Zhenming and Yang, Ming-Jay and Finkbeiner, Jan and
                      Siegel, Sebastian and Strachan, John Paul and Neftci, Emre},
      title        = {{T}he {O}uroboros of {M}emristors: {N}eural {N}etworks
                      {F}acilitating {M}emristor {P}rogramming},
      publisher    = {arXiv},
      reportid     = {FZJ-2025-01085},
      year         = {2024},
      abstract     = {Memristive devices hold promise to improve the scale and
                      efficiency of machine learning and neuromorphic hardware,
                      thanks to their compact size, low power consumption, and the
                      ability to perform matrix multiplications in constant time.
                      However, on-chip training with memristor arrays still faces
                      challenges, including device-to-device and cycle-to-cycle
                      variations, switching non-linearity, and especially SET and
                      RESET asymmetry. To combat device non-linearity and
                      asymmetry, we propose to program memristors by harnessing
                      neural networks that map desired conductance updates to the
                      required pulse times. With our method, approximately $95\%$
                      of devices can be programmed within a relative percentage
                      difference of $+-50\%$ from the target conductance after
                      just one attempt. Our approach substantially reduces
                      memristor programming delays compared to traditional
                      write-and-verify methods, presenting an advantageous
                      solution for on-chip training scenarios. Furthermore, our
                      proposed neural network can be accelerated by memristor
                      arrays upon deployment, providing assistance while reducing
                      hardware overhead compared with previous works. This work
                      contributes significantly to the practical application of
                      memristors, particularly in reducing delays in memristor
                      programming. It also envisions the future development of
                      memristor-based machine learning accelerators.},
      keywords     = {Emerging Technologies (cs.ET) (Other) / FOS: Computer and
                      information sciences (Other)},
      cin          = {PGI-15 / PGI-14},
      cid          = {I:(DE-Juel1)PGI-15-20210701 / I:(DE-Juel1)PGI-14-20210412},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF 16ME0400
                      - Verbundprojekt: Neuro-inspirierte Technologien der
                      künstlichen Intelligenz für die Elektronik der Zukunft -
                      NEUROTEC II - (16ME0400) / BMBF 03ZU1106CA - NeuroSys:
                      Algorithm-Hardware Co-Design (Projekt C) - A (03ZU1106CA) /
                      BMBF 03ZU1106CB - NeuroSys: Algorithm-Hardware Co-Design
                      (Projekt C) - B (BMBF-03ZU1106CB)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(BMBF)16ME0400 / G:(BMBF)03ZU1106CA
                      / G:(DE-Juel1)BMBF-03ZU1106CB},
      typ          = {PUB:(DE-HGF)25},
      doi          = {10.48550/arXiv.2403.06712},
      url          = {https://juser.fz-juelich.de/record/1038036},
}