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@MASTERSTHESIS{Yenilen:1038457,
      author       = {Yenilen, Berat},
      title        = {{I}nvestigating {P}recision {E}rrors on {D}-{W}ave's
                      {A}dvantage {S}ystem {P}rocessor using {Q}uantum {A}nnealing
                      {C}orrection with {T}riangle {C}opies},
      school       = {Rheinisch-Westfälische Technische Hochschule Aachen},
      type         = {Masterarbeit},
      reportid     = {FZJ-2025-01453},
      pages        = {64},
      year         = {2024},
      note         = {Masterarbeit, Rheinisch-Westfälische Technische Hochschule
                      Aachen, 2024},
      cin          = {JSC},
      cid          = {I:(DE-Juel1)JSC-20090406},
      pnm          = {5111 - Domain-Specific Simulation $\&$ Data Life Cycle Labs
                      (SDLs) and Research Groups (POF4-511)},
      pid          = {G:(DE-HGF)POF4-5111},
      typ          = {PUB:(DE-HGF)19},
      url          = {https://juser.fz-juelich.de/record/1038457},
}