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| Hauptseite > Publikationsdatenbank > Exploring Processor Micro-architectures Optimised for BLAS3 Micro-kernels > print |
| Hauptseite > Publikationsdatenbank > Exploring Processor Micro-architectures Optimised for BLAS3 Micro-kernels > print |
| 001 | 1038510 | ||
| 005 | 20250203124521.0 | ||
| 020 | _ | _ | |a 978-3-031-69765-4 (print) |
| 020 | _ | _ | |a 978-3-031-69766-1 (electronic) |
| 024 | 7 | _ | |a 10.1007/978-3-031-69766-1_4 |2 doi |
| 024 | 7 | _ | |a 0302-9743 |2 ISSN |
| 024 | 7 | _ | |a 1611-3349 |2 ISSN |
| 024 | 7 | _ | |a WOS:001308370400004 |2 WOS |
| 037 | _ | _ | |a FZJ-2025-01495 |
| 100 | 1 | _ | |a Nassyr, Stepan |0 P:(DE-Juel1)172888 |b 0 |u fzj |
| 111 | 2 | _ | |a 30th European Conference on Parallel and Distributed Processing |g Euro-Par 2024 |c Madrid |d 2024-08-26 - 2024-08-30 |w Spain |
| 245 | _ | _ | |a Exploring Processor Micro-architectures Optimised for BLAS3 Micro-kernels |
| 260 | _ | _ | |a Cham |c 2024 |b Springer Nature Switzerland |
| 295 | 1 | 0 | |a Euro-Par 2024: Parallel Processing |
| 300 | _ | _ | |a 47 - 61 |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
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| 490 | 0 | _ | |a Lecture Notes in Computer Science |v 14802 |
| 520 | _ | _ | |a Dense matrix-matrix operations are relevant for a broad range of numerical applications, e.g. for implementing deep neural networks. Past research has led to a good understanding of how these operations can be mapped in a generic manner on typical processor architectures with multiple cache levels such that near-optimal performance can be reached. However, while commonly used micro-architectures are typically suitable for such operations, their architectural parameters need to be suitably tuned. The performance of highly optimised implementations of these operations relies on micro-kernels that are often handwritten. Given the increased variety of instruction set architectures and SIMD instruction extensions, this becomes challenging. In this paper, wepresent and implement a methodology for an exhaustive exploration of a processor core micro-architecture design space based on gem5 simulations. Furthermore, we present a tool for generating efficiently vectorised code leveraging Arm’s SVE and RISC-V’s RVV instructions. It enables automatisation of the generation of micro-kernels and, therefore, the generation of a large range of such kernels. The results provide insights both, to micro-architecture architects as well as micro-kernel developers. The assembler generator is open-sourced and the simulation data is availableas supplementary material. |
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| 700 | 1 | _ | |a Pleiter, Dirk |0 P:(DE-Juel1)144441 |b 1 |e Corresponding author |
| 770 | _ | _ | |z 978-3-031-69765-4=978-3-031-69766-1 |
| 773 | _ | _ | |a 10.1007/978-3-031-69766-1_4 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1038510/files/978-3-031-69766-1.pdf |y Restricted |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1038510/files/Preprint.pdf |y Restricted |
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| 914 | 1 | _ | |y 2024 |
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