TY  - JOUR
AU  - Yu, Jiaao
AU  - Manea, Paul
AU  - Hizzani, Mohammad
AU  - Ameli Kalkhouran, Sara
AU  - Strachan, John Paul
TI  - A Memristor Variation-Aware Analog Memristor Programming Circuit for Associative Memories
JO  - 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
VL  - 4
PB  - IEEE
M1  - FZJ-2025-01705
SP  - 1-4
PY  - 2024
AB  - In the emerging realm such as in-memory computing and associative memories, the application of memristors necessitates the development of high-performance programming circuits for effective weight updates. The conventional Program-Verify (PV) method requires complex memory peripherals and data converters, which is a major bottleneck for area and power efficiency. Moreover, memristor variability critically undermines the efficacy of AI applications utilizing memristive technology. Addressing these challenges, this paper introduces a novel analog memristor programming circuit that takes memristor variations into account. Leveraging the TSMC 28nm process PDK and the JART VCM vlb var memristor model for simulations, our circuit achieves ±1 µS error margin for over 98.5% of programming results without using ADCs. When contrasted with preceding studies, the proposed solution not only reduces the programming settling time by 15.0% to 87.5% but also exhibits comparable performance to the PV method designed with the same semiconductor and memristor technology.
T2  - 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
CY  - 18 Nov 2024 - 20 Nov 2024, Nancy (France)
Y2  - 18 Nov 2024 - 20 Nov 2024
M2  - Nancy, France
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)16
UR  - <Go to ISI:>//WOS:001445799800062
DO  - DOI:10.1109/ICECS61496.2024.10848806
UR  - https://juser.fz-juelich.de/record/1038894
ER  -