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| Hauptseite > Publikationsdatenbank > A Memristor Variation-Aware Analog Memristor Programming Circuit for Associative Memories > print |
| Hauptseite > Publikationsdatenbank > A Memristor Variation-Aware Analog Memristor Programming Circuit for Associative Memories > print |
| 001 | 1038894 | ||
| 005 | 20250414120457.0 | ||
| 024 | 7 | _ | |a 10.1109/ICECS61496.2024.10848806 |2 doi |
| 024 | 7 | _ | |a WOS:001445799800062 |2 WOS |
| 037 | _ | _ | |a FZJ-2025-01705 |
| 100 | 1 | _ | |a Yu, Jiaao |0 P:(DE-HGF)0 |b 0 |
| 111 | 2 | _ | |a 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) |c Nancy |d 2024-11-18 - 2024-11-20 |w France |
| 245 | _ | _ | |a A Memristor Variation-Aware Analog Memristor Programming Circuit for Associative Memories |
| 260 | _ | _ | |c 2024 |b IEEE |
| 336 | 7 | _ | |a article |2 DRIVER |
| 336 | 7 | _ | |a Contribution to a conference proceedings |0 PUB:(DE-HGF)8 |2 PUB:(DE-HGF) |m contrib |
| 336 | 7 | _ | |a Output Types/Journal article |2 DataCite |
| 336 | 7 | _ | |a Journal Article |b journal |m journal |0 PUB:(DE-HGF)16 |s 1738850345_13173 |2 PUB:(DE-HGF) |
| 336 | 7 | _ | |a ARTICLE |2 BibTeX |
| 336 | 7 | _ | |a JOURNAL_ARTICLE |2 ORCID |
| 336 | 7 | _ | |a Journal Article |0 0 |2 EndNote |
| 520 | _ | _ | |a In the emerging realm such as in-memory computing and associative memories, the application of memristors necessitates the development of high-performance programming circuits for effective weight updates. The conventional Program-Verify (PV) method requires complex memory peripherals and data converters, which is a major bottleneck for area and power efficiency. Moreover, memristor variability critically undermines the efficacy of AI applications utilizing memristive technology. Addressing these challenges, this paper introduces a novel analog memristor programming circuit that takes memristor variations into account. Leveraging the TSMC 28nm process PDK and the JART VCM vlb var memristor model for simulations, our circuit achieves ±1 µS error margin for over 98.5% of programming results without using ADCs. When contrasted with preceding studies, the proposed solution not only reduces the programming settling time by 15.0% to 87.5% but also exhibits comparable performance to the PV method designed with the same semiconductor and memristor technology. |
| 536 | _ | _ | |a 5234 - Emerging NC Architectures (POF4-523) |0 G:(DE-HGF)POF4-5234 |c POF4-523 |f POF IV |x 0 |
| 536 | _ | _ | |a 5233 - Memristive Materials and Devices (POF4-523) |0 G:(DE-HGF)POF4-5233 |c POF4-523 |f POF IV |x 1 |
| 588 | _ | _ | |a Dataset connected to CrossRef Conference |
| 700 | 1 | _ | |a Manea, Paul |0 P:(DE-Juel1)192242 |b 1 |u fzj |
| 700 | 1 | _ | |a Hizzani, Mohammad |0 P:(DE-Juel1)190961 |b 2 |u fzj |
| 700 | 1 | _ | |a Ameli Kalkhouran, Sara |0 P:(DE-Juel1)191419 |b 3 |u fzj |
| 700 | 1 | _ | |a Strachan, John Paul |0 P:(DE-Juel1)188145 |b 4 |u fzj |
| 770 | _ | _ | |z 979-8-3503-7721-7 |
| 773 | _ | _ | |a 10.1109/ICECS61496.2024.10848806 |p 1-4 |v 4 |y 2024 |t 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) |
| 856 | 4 | _ | |u https://ieeexplore.ieee.org/abstract/document/10848806 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1038894/files/A_Memristor_Variation-Aware_Analog_Memristor_Programming_Circuit_for_Associative_Memories.pdf |y Restricted |
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| 914 | 1 | _ | |y 2024 |
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