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001038905 0247_ $$2datacite_doi$$a10.34734/FZJ-2025-01715
001038905 037__ $$aFZJ-2025-01715
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001038905 1001_ $$0P:(DE-Juel1)203161$$aZhao, Wei$$b0
001038905 245__ $$aAlgorithm Development For AnAutomated Memristor Control On ANeuromorphic Demonstrator Chip$$f - 2025-08-31
001038905 260__ $$c2024
001038905 300__ $$a161
001038905 3367_ $$2DataCite$$aOutput Types/Supervised Student Publication
001038905 3367_ $$02$$2EndNote$$aThesis
001038905 3367_ $$2BibTeX$$aMASTERSTHESIS
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001038905 3367_ $$0PUB:(DE-HGF)19$$2PUB:(DE-HGF)$$aMaster Thesis$$bmaster$$mmaster$$s1739262885_5410
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001038905 502__ $$aMasterarbeit, TU Munich, 2024$$bMasterarbeit$$cTU Munich$$d2024
001038905 520__ $$aAdvancements on in-memory technology have positioned memristors at the fore-front of non-volatile memory applications, necessitating precise control mecha-nisms to accurately program memristor cells to their respective states. Whilecommercial memristor applications primarily focus on binary data storage, theunique requirements of neuromorphic computing necessitate the ability to handlea wide range of analog values for synaptic emulation. This thesis explores theutilization of a RISC-V processor and pulse-width modulation generators to con-figure registers for analog conductance control within a crossbar memristor arrayarchitecture. The system incorporates mechanisms to read back the programmedresistance values using an analog-to-digital converter, compare these resistance val-ues to the expected outcomes, and minimize any discrepancies, thereby facilitatingaccurate voltage and current mode operations.The core contribution of this research is the development of a flexible and effi-cient control algorithm, along with an error correction algorithm specifically de-signed for the RISC-V architecture. By leveraging these algorithms, the systemcan dynamically adjust and correct the states of memristor cells, ensuring highprecision and reliability in memory operations tailored for neuromorphic comput-ing.To validate the control signals generated by the proposed algorithms, a UniversalVerification Methodology Framework testbench is employed. This comprehensiveverification process ensures that the control mechanisms are accurate and reliablebefore proceeding to hardware implementation.The results from our study indicate significant enhancements in control effi-ciency, demonstrating the potential for seamless integration of RISC-V processorswith memristor technology. This integration paves the way for advanced non-volatile memory solutions that are both robust and highly efficient, marking anotable step forward in the field of memory technology and specifically addressingthe needs of neuromorphic computing.
001038905 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001038905 536__ $$0G:(DE-82)BMBF-16ME0398K$$aBMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)$$cBMBF-16ME0398K$$x1
001038905 8564_ $$uhttps://juser.fz-juelich.de/record/1038905/files/Master%20thesis%20%3A%20Algorithm%20Development%20For%20An%20Automated%20Memristor%20Control%20On%20A%20Neuromorphic%20Demonstrator%20Chip.pdf$$yOpenAccess
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001038905 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001038905 9141_ $$y2024
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001038905 9201_ $$0I:(DE-Juel1)PGI-4-20110106$$kPGI-4$$lIntegrated Computing Architectures$$x0
001038905 9201_ $$0I:(DE-Juel1)ZEA-2-20090406$$kZEA-2$$lZentralinstitut für Elektronik$$x1
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