001     1038905
005     20250220092006.0
024 7 _ |a 10.34734/FZJ-2025-01715
|2 datacite_doi
037 _ _ |a FZJ-2025-01715
041 _ _ |a English
100 1 _ |a Zhao, Wei
|0 P:(DE-Juel1)203161
|b 0
245 _ _ |a Algorithm Development For AnAutomated Memristor Control On ANeuromorphic Demonstrator Chip
|f - 2025-08-31
260 _ _ |c 2024
300 _ _ |a 161
336 7 _ |a Output Types/Supervised Student Publication
|2 DataCite
336 7 _ |a Thesis
|0 2
|2 EndNote
336 7 _ |a MASTERSTHESIS
|2 BibTeX
336 7 _ |a masterThesis
|2 DRIVER
336 7 _ |a Master Thesis
|b master
|m master
|0 PUB:(DE-HGF)19
|s 1739262885_5410
|2 PUB:(DE-HGF)
336 7 _ |a SUPERVISED_STUDENT_PUBLICATION
|2 ORCID
502 _ _ |a Masterarbeit, TU Munich, 2024
|c TU Munich
|b Masterarbeit
|d 2024
520 _ _ |a Advancements on in-memory technology have positioned memristors at the fore-front of non-volatile memory applications, necessitating precise control mecha-nisms to accurately program memristor cells to their respective states. Whilecommercial memristor applications primarily focus on binary data storage, theunique requirements of neuromorphic computing necessitate the ability to handlea wide range of analog values for synaptic emulation. This thesis explores theutilization of a RISC-V processor and pulse-width modulation generators to con-figure registers for analog conductance control within a crossbar memristor arrayarchitecture. The system incorporates mechanisms to read back the programmedresistance values using an analog-to-digital converter, compare these resistance val-ues to the expected outcomes, and minimize any discrepancies, thereby facilitatingaccurate voltage and current mode operations.The core contribution of this research is the development of a flexible and effi-cient control algorithm, along with an error correction algorithm specifically de-signed for the RISC-V architecture. By leveraging these algorithms, the systemcan dynamically adjust and correct the states of memristor cells, ensuring highprecision and reliability in memory operations tailored for neuromorphic comput-ing.To validate the control signals generated by the proposed algorithms, a UniversalVerification Methodology Framework testbench is employed. This comprehensiveverification process ensures that the control mechanisms are accurate and reliablebefore proceeding to hardware implementation.The results from our study indicate significant enhancements in control effi-ciency, demonstrating the potential for seamless integration of RISC-V processorswith memristor technology. This integration paves the way for advanced non-volatile memory solutions that are both robust and highly efficient, marking anotable step forward in the field of memory technology and specifically addressingthe needs of neuromorphic computing.
536 _ _ |a 5234 - Emerging NC Architectures (POF4-523)
|0 G:(DE-HGF)POF4-5234
|c POF4-523
|f POF IV
|x 0
536 _ _ |a BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)
|0 G:(DE-82)BMBF-16ME0398K
|c BMBF-16ME0398K
|x 1
856 4 _ |u https://juser.fz-juelich.de/record/1038905/files/Master%20thesis%20%3A%20Algorithm%20Development%20For%20An%20Automated%20Memristor%20Control%20On%20A%20Neuromorphic%20Demonstrator%20Chip.pdf
|y OpenAccess
909 C O |o oai:juser.fz-juelich.de:1038905
|p openaire
|p open_access
|p VDB
|p driver
|p dnbdelivery
913 1 _ |a DE-HGF
|b Key Technologies
|l Natural, Artificial and Cognitive Information Processing
|1 G:(DE-HGF)POF4-520
|0 G:(DE-HGF)POF4-523
|3 G:(DE-HGF)POF4
|2 G:(DE-HGF)POF4-500
|4 G:(DE-HGF)POF
|v Neuromorphic Computing and Network Dynamics
|9 G:(DE-HGF)POF4-5234
|x 0
914 1 _ |y 2024
915 _ _ |a OpenAccess
|0 StatID:(DE-HGF)0510
|2 StatID
920 _ _ |l yes
920 1 _ |0 I:(DE-Juel1)PGI-4-20110106
|k PGI-4
|l Integrated Computing Architectures
|x 0
920 1 _ |0 I:(DE-Juel1)ZEA-2-20090406
|k ZEA-2
|l Zentralinstitut für Elektronik
|x 1
980 1 _ |a FullTexts
980 _ _ |a master
980 _ _ |a VDB
980 _ _ |a UNRESTRICTED
980 _ _ |a I:(DE-Juel1)PGI-4-20110106
980 _ _ |a I:(DE-Juel1)ZEA-2-20090406


LibraryCollectionCLSMajorCLSMinorLanguageAuthor
Marc 21