001039471 001__ 1039471
001039471 005__ 20250414120442.0
001039471 0247_ $$2doi$$a10.1109/ICECS61496.2024.10848856
001039471 0247_ $$2datacite_doi$$a10.34734/FZJ-2025-01765
001039471 0247_ $$2WOS$$aWOS:001445799800077
001039471 037__ $$aFZJ-2025-01765
001039471 1001_ $$0P:(DE-Juel1)184396$$aFirdauzi, Anugerah$$b0$$eCorresponding author$$ufzj
001039471 1112_ $$a2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)$$cNancy$$d2024-11-18 - 2024-11-20$$wFrance
001039471 245__ $$aPower Efficient Current-Mode SAR ADC for Memristor Readout in 28 nm CMOS
001039471 260__ $$bIEEE$$c2024
001039471 300__ $$a1-4
001039471 3367_ $$2ORCID$$aCONFERENCE_PAPER
001039471 3367_ $$033$$2EndNote$$aConference Paper
001039471 3367_ $$2BibTeX$$aINPROCEEDINGS
001039471 3367_ $$2DRIVER$$aconferenceObject
001039471 3367_ $$2DataCite$$aOutput Types/Conference Paper
001039471 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1739872224_31425
001039471 520__ $$aThis paper introduces a current-mode Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) for the current readout in a memristor based vector-matrix multiplication for computing-in-memory. The proposed method employs direct current measurement scheme using an open-loop transimpedance input stage. As the types and resistance values of the memristors change, so does the output current of the array, along with the voltage range, especially with multilevel signal processing. Therefore, we propose an ADC where the dynamic range can be tuned between 0.4 and 1.28mA while consuming 1 to 2.73 m W of power. While the memristor array operate at a 1.8 V power supply for SET and RESET operation, the ADC can be implemented using a 0.9 V power supply as we employs a voltage-regulation loop that can work with less than 0.8 V voltage during current readout mode. This enables the ADC to be implemented using core CMOS devices, reducing power and area consumption. The ADC features 6 bit resolution and is implemented in a 28 nm CMOS bulk technology. It can achieve a data-conversion rate of up to 50 MSps.
001039471 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001039471 536__ $$0G:(DE-82)BMBF-16ME0398K$$aBMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)$$cBMBF-16ME0398K$$x1
001039471 588__ $$aDataset connected to CrossRef Conference
001039471 7001_ $$0P:(DE-Juel1)159350$$aGrewing, Christian$$b1$$ufzj
001039471 7001_ $$0P:(DE-Juel1)176328$$aAshok, Arun$$b2$$ufzj
001039471 7001_ $$0P:(DE-Juel1)187432$$aKusuma, Sabitha$$b3$$ufzj
001039471 7001_ $$0P:(DE-Juel1)184687$$aWinterberg, Kay$$b4$$ufzj
001039471 7001_ $$0P:(DE-Juel1)145837$$aZambanini, André$$b5$$ufzj
001039471 7001_ $$0P:(DE-Juel1)142562$$avan Waasen, Stefan$$b6
001039471 773__ $$a10.1109/ICECS61496.2024.10848856
001039471 8564_ $$uhttps://ieeexplore.ieee.org/document/10848856
001039471 8564_ $$uhttps://juser.fz-juelich.de/record/1039471/files/ADC_IEEE_ICECS_2024_Revised%20%282%29.pdf$$yOpenAccess
001039471 909CO $$ooai:juser.fz-juelich.de:1039471$$pdnbdelivery$$pdriver$$pVDB$$popen_access$$popenaire
001039471 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)184396$$aForschungszentrum Jülich$$b0$$kFZJ
001039471 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)159350$$aForschungszentrum Jülich$$b1$$kFZJ
001039471 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)176328$$aForschungszentrum Jülich$$b2$$kFZJ
001039471 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)187432$$aForschungszentrum Jülich$$b3$$kFZJ
001039471 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)184687$$aForschungszentrum Jülich$$b4$$kFZJ
001039471 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)145837$$aForschungszentrum Jülich$$b5$$kFZJ
001039471 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)142562$$aForschungszentrum Jülich$$b6$$kFZJ
001039471 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001039471 9141_ $$y2024
001039471 915__ $$0StatID:(DE-HGF)0510$$2StatID$$aOpenAccess
001039471 920__ $$lyes
001039471 9201_ $$0I:(DE-Juel1)PGI-4-20110106$$kPGI-4$$lIntegrated Computing Architectures$$x0
001039471 9201_ $$0I:(DE-Juel1)ZEA-2-20090406$$kZEA-2$$lZentralinstitut für Elektronik$$x1
001039471 980__ $$acontrib
001039471 980__ $$aVDB
001039471 980__ $$aUNRESTRICTED
001039471 980__ $$aI:(DE-Juel1)PGI-4-20110106
001039471 980__ $$aI:(DE-Juel1)ZEA-2-20090406
001039471 9801_ $$aFullTexts