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@INPROCEEDINGS{Firdauzi:1039471,
      author       = {Firdauzi, Anugerah and Grewing, Christian and Ashok, Arun
                      and Kusuma, Sabitha and Winterberg, Kay and Zambanini,
                      André and van Waasen, Stefan},
      title        = {{P}ower {E}fficient {C}urrent-{M}ode {SAR} {ADC} for
                      {M}emristor {R}eadout in 28 nm {CMOS}},
      publisher    = {IEEE},
      reportid     = {FZJ-2025-01765},
      pages        = {1-4},
      year         = {2024},
      abstract     = {This paper introduces a current-mode
                      Successive-Approximation Register Analog-to-Digital
                      Converter (SAR ADC) for the current readout in a memristor
                      based vector-matrix multiplication for computing-in-memory.
                      The proposed method employs direct current measurement
                      scheme using an open-loop transimpedance input stage. As the
                      types and resistance values of the memristors change, so
                      does the output current of the array, along with the voltage
                      range, especially with multilevel signal processing.
                      Therefore, we propose an ADC where the dynamic range can be
                      tuned between 0.4 and 1.28mA while consuming 1 to 2.73 m W
                      of power. While the memristor array operate at a 1.8 V power
                      supply for SET and RESET operation, the ADC can be
                      implemented using a 0.9 V power supply as we employs a
                      voltage-regulation loop that can work with less than 0.8 V
                      voltage during current readout mode. This enables the ADC to
                      be implemented using core CMOS devices, reducing power and
                      area consumption. The ADC features 6 bit resolution and is
                      implemented in a 28 nm CMOS bulk technology. It can achieve
                      a data-conversion rate of up to 50 MSps.},
      month         = {Nov},
      date          = {2024-11-18},
      organization  = {2024 31st IEEE International
                       Conference on Electronics, Circuits and
                       Systems (ICECS), Nancy (France), 18 Nov
                       2024 - 20 Nov 2024},
      cin          = {PGI-4 / ZEA-2},
      cid          = {I:(DE-Juel1)PGI-4-20110106 / I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF
                      16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)8},
      UT           = {WOS:001445799800077},
      doi          = {10.1109/ICECS61496.2024.10848856},
      url          = {https://juser.fz-juelich.de/record/1039471},
}