guest ::
| Home > Publications database > Power Efficient Current-Mode SAR ADC for Memristor Readout in 28 nm CMOS > print |
| Home > Publications database > Power Efficient Current-Mode SAR ADC for Memristor Readout in 28 nm CMOS > print |
| 001 | 1039471 | ||
| 005 | 20250414120442.0 | ||
| 024 | 7 | _ | |a 10.1109/ICECS61496.2024.10848856 |2 doi |
| 024 | 7 | _ | |a 10.34734/FZJ-2025-01765 |2 datacite_doi |
| 024 | 7 | _ | |a WOS:001445799800077 |2 WOS |
| 037 | _ | _ | |a FZJ-2025-01765 |
| 100 | 1 | _ | |a Firdauzi, Anugerah |0 P:(DE-Juel1)184396 |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) |c Nancy |d 2024-11-18 - 2024-11-20 |w France |
| 245 | _ | _ | |a Power Efficient Current-Mode SAR ADC for Memristor Readout in 28 nm CMOS |
| 260 | _ | _ | |c 2024 |b IEEE |
| 300 | _ | _ | |a 1-4 |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
| 336 | 7 | _ | |a conferenceObject |2 DRIVER |
| 336 | 7 | _ | |a Output Types/Conference Paper |2 DataCite |
| 336 | 7 | _ | |a Contribution to a conference proceedings |b contrib |m contrib |0 PUB:(DE-HGF)8 |s 1739872224_31425 |2 PUB:(DE-HGF) |
| 520 | _ | _ | |a This paper introduces a current-mode Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) for the current readout in a memristor based vector-matrix multiplication for computing-in-memory. The proposed method employs direct current measurement scheme using an open-loop transimpedance input stage. As the types and resistance values of the memristors change, so does the output current of the array, along with the voltage range, especially with multilevel signal processing. Therefore, we propose an ADC where the dynamic range can be tuned between 0.4 and 1.28mA while consuming 1 to 2.73 m W of power. While the memristor array operate at a 1.8 V power supply for SET and RESET operation, the ADC can be implemented using a 0.9 V power supply as we employs a voltage-regulation loop that can work with less than 0.8 V voltage during current readout mode. This enables the ADC to be implemented using core CMOS devices, reducing power and area consumption. The ADC features 6 bit resolution and is implemented in a 28 nm CMOS bulk technology. It can achieve a data-conversion rate of up to 50 MSps. |
| 536 | _ | _ | |a 5234 - Emerging NC Architectures (POF4-523) |0 G:(DE-HGF)POF4-5234 |c POF4-523 |f POF IV |x 0 |
| 536 | _ | _ | |a BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K) |0 G:(DE-82)BMBF-16ME0398K |c BMBF-16ME0398K |x 1 |
| 588 | _ | _ | |a Dataset connected to CrossRef Conference |
| 700 | 1 | _ | |a Grewing, Christian |0 P:(DE-Juel1)159350 |b 1 |u fzj |
| 700 | 1 | _ | |a Ashok, Arun |0 P:(DE-Juel1)176328 |b 2 |u fzj |
| 700 | 1 | _ | |a Kusuma, Sabitha |0 P:(DE-Juel1)187432 |b 3 |u fzj |
| 700 | 1 | _ | |a Winterberg, Kay |0 P:(DE-Juel1)184687 |b 4 |u fzj |
| 700 | 1 | _ | |a Zambanini, André |0 P:(DE-Juel1)145837 |b 5 |u fzj |
| 700 | 1 | _ | |a van Waasen, Stefan |0 P:(DE-Juel1)142562 |b 6 |
| 773 | _ | _ | |a 10.1109/ICECS61496.2024.10848856 |
| 856 | 4 | _ | |u https://ieeexplore.ieee.org/document/10848856 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1039471/files/ADC_IEEE_ICECS_2024_Revised%20%282%29.pdf |y OpenAccess |
| 909 | C | O | |o oai:juser.fz-juelich.de:1039471 |p openaire |p open_access |p VDB |p driver |p dnbdelivery |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 0 |6 P:(DE-Juel1)184396 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 1 |6 P:(DE-Juel1)159350 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 2 |6 P:(DE-Juel1)176328 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 3 |6 P:(DE-Juel1)187432 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 4 |6 P:(DE-Juel1)184687 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 5 |6 P:(DE-Juel1)145837 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 6 |6 P:(DE-Juel1)142562 |
| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Natural, Artificial and Cognitive Information Processing |1 G:(DE-HGF)POF4-520 |0 G:(DE-HGF)POF4-523 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Neuromorphic Computing and Network Dynamics |9 G:(DE-HGF)POF4-5234 |x 0 |
| 914 | 1 | _ | |y 2024 |
| 915 | _ | _ | |a OpenAccess |0 StatID:(DE-HGF)0510 |2 StatID |
| 920 | _ | _ | |l yes |
| 920 | 1 | _ | |0 I:(DE-Juel1)PGI-4-20110106 |k PGI-4 |l Integrated Computing Architectures |x 0 |
| 920 | 1 | _ | |0 I:(DE-Juel1)ZEA-2-20090406 |k ZEA-2 |l Zentralinstitut für Elektronik |x 1 |
| 980 | _ | _ | |a contrib |
| 980 | _ | _ | |a VDB |
| 980 | _ | _ | |a UNRESTRICTED |
| 980 | _ | _ | |a I:(DE-Juel1)PGI-4-20110106 |
| 980 | _ | _ | |a I:(DE-Juel1)ZEA-2-20090406 |
| 980 | 1 | _ | |a FullTexts |
| Library | Collection | CLSMajor | CLSMinor | Language | Author |
|---|