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@INPROCEEDINGS{Firdauzi:1039472,
      author       = {Firdauzi, Anugerah and Grewing, Christian and Ashok, Arun
                      and Zambanini, Andre and van Waasen, Stefan},
      title        = {{A} {C}urrent-{M}ode {SAR} {ADC} for {M}emristor {R}eadout
                      in 28nm {CMOS}},
      reportid     = {FZJ-2025-01766},
      year         = {2024},
      abstract     = {Computing in Memory (CIM) is a computing paradigm to
                      overcome the von Neumann bottleneck of traditional
                      computerarchitectures [1]. A possible implementation uses
                      memristor crossbar arrays, which store information as
                      resistance, toperform parallel vector-matrix multiplication
                      (VMM). In this structure, digital to analog converters
                      (DACs) provide inputvoltages to the crossbar rows where the
                      output currents are then measured by analog to digital
                      converters (ADCs). Therefore,both converter circuits play an
                      important role when optimizing the speed and power
                      consumption in the operation.In this research, we propose a
                      single-ended current-mode ADC, as shown in Fig. 1, which can
                      directly measure the inputcurrent from the memristor array
                      without the need for any transconductance amplifier (TIA),
                      sampling-and-hold circuit, oreven charge integration method
                      that is often used for current measurement [2][3]. This ADC
                      measures single-ended inputand is implemented in
                      pseudo-differential manner to enhance its robustness against
                      noise and disturbance. In this ADC, theinput current is
                      first compared with half of the reference current provided
                      by transistor M5 for the most significant bit
                      (MSB)conversion. Then, the subtracted current enters the
                      differential structure formed by transistor M6-9 where they
                      then convertedinto voltage difference across the 350 Ω load
                      resistance. Data conversion is then performed using an array
                      of current-steeringDAC that operate according to the
                      successive-approximation register (SAR) algorithm. The bias
                      for this ADC isimplemented as cascoded current source and
                      can be used for multiple ADC core circuits. Additionally,
                      the dynamic rangeof the ADC can be tuned by simply changing
                      the reference current IREF biasing transistor M0,1.In this
                      work, a 2x2 CIM array is implemented by using 28 nm CMOS
                      technology. As shown in Fig.2, this chip has the sizeof 1.4
                      mm2 and consists of the control circuit for memristor
                      interface followed by two ADCs. A RISC-V processor is
                      alsoimplemented to control the circuit and direct access
                      available through a JTAG programming interface. The ADC is
                      designedto have dynamic range of 1.28 mA with 6 bit
                      resolution and can work with speed up to 100 MSps while
                      consuming lessthan 3 mW power from 0.9 V power supply. Each
                      ADC occupies less than 0.005 mm2 area and thus suitable to
                      beimplemented multiple times as column ADCs. These ADCs also
                      have the capability of choosing the source of input
                      eitherfrom memristor array or from external input to make
                      the measurement and characterization process easier.},
      month         = {Nov},
      date          = {2024-11-10},
      organization  = {MEMRISYS 2024, Seoul (South Korea), 10
                       Nov 2024 - 13 Nov 2024},
      cin          = {PGI-4 / ZEA-2},
      cid          = {I:(DE-Juel1)PGI-4-20110106 / I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF
                      16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)1},
      doi          = {10.34734/FZJ-2025-01766},
      url          = {https://juser.fz-juelich.de/record/1039472},
}