guest ::
| Home > Publications database > A Current-Mode SAR ADC for Memristor Readout in 28nm CMOS > print |
| 001 | 1039472 | ||
| 005 | 20250220092006.0 | ||
| 024 | 7 | _ | |a 10.34734/FZJ-2025-01766 |2 datacite_doi |
| 037 | _ | _ | |a FZJ-2025-01766 |
| 100 | 1 | _ | |a Firdauzi, Anugerah |0 P:(DE-Juel1)184396 |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a MEMRISYS 2024 |c Seoul |d 2024-11-10 - 2024-11-13 |w South Korea |
| 245 | _ | _ | |a A Current-Mode SAR ADC for Memristor Readout in 28nm CMOS |
| 260 | _ | _ | |c 2024 |
| 336 | 7 | _ | |a Abstract |b abstract |m abstract |0 PUB:(DE-HGF)1 |s 1739866041_1701 |2 PUB:(DE-HGF) |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
| 336 | 7 | _ | |a conferenceObject |2 DRIVER |
| 336 | 7 | _ | |a Output Types/Conference Abstract |2 DataCite |
| 336 | 7 | _ | |a OTHER |2 ORCID |
| 520 | _ | _ | |a Computing in Memory (CIM) is a computing paradigm to overcome the von Neumann bottleneck of traditional computerarchitectures [1]. A possible implementation uses memristor crossbar arrays, which store information as resistance, toperform parallel vector-matrix multiplication (VMM). In this structure, digital to analog converters (DACs) provide inputvoltages to the crossbar rows where the output currents are then measured by analog to digital converters (ADCs). Therefore,both converter circuits play an important role when optimizing the speed and power consumption in the operation.In this research, we propose a single-ended current-mode ADC, as shown in Fig. 1, which can directly measure the inputcurrent from the memristor array without the need for any transconductance amplifier (TIA), sampling-and-hold circuit, oreven charge integration method that is often used for current measurement [2][3]. This ADC measures single-ended inputand is implemented in pseudo-differential manner to enhance its robustness against noise and disturbance. In this ADC, theinput current is first compared with half of the reference current provided by transistor M5 for the most significant bit (MSB)conversion. Then, the subtracted current enters the differential structure formed by transistor M6-9 where they then convertedinto voltage difference across the 350 Ω load resistance. Data conversion is then performed using an array of current-steeringDAC that operate according to the successive-approximation register (SAR) algorithm. The bias for this ADC isimplemented as cascoded current source and can be used for multiple ADC core circuits. Additionally, the dynamic rangeof the ADC can be tuned by simply changing the reference current IREF biasing transistor M0,1.In this work, a 2x2 CIM array is implemented by using 28 nm CMOS technology. As shown in Fig.2, this chip has the sizeof 1.4 mm2 and consists of the control circuit for memristor interface followed by two ADCs. A RISC-V processor is alsoimplemented to control the circuit and direct access available through a JTAG programming interface. The ADC is designedto have dynamic range of 1.28 mA with 6 bit resolution and can work with speed up to 100 MSps while consuming lessthan 3 mW power from 0.9 V power supply. Each ADC occupies less than 0.005 mm2 area and thus suitable to beimplemented multiple times as column ADCs. These ADCs also have the capability of choosing the source of input eitherfrom memristor array or from external input to make the measurement and characterization process easier. |
| 536 | _ | _ | |a 5234 - Emerging NC Architectures (POF4-523) |0 G:(DE-HGF)POF4-5234 |c POF4-523 |f POF IV |x 0 |
| 536 | _ | _ | |a BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K) |0 G:(DE-82)BMBF-16ME0398K |c BMBF-16ME0398K |x 1 |
| 700 | 1 | _ | |a Grewing, Christian |0 P:(DE-Juel1)159350 |b 1 |
| 700 | 1 | _ | |a Ashok, Arun |0 P:(DE-Juel1)176328 |b 2 |
| 700 | 1 | _ | |a Zambanini, Andre |0 P:(DE-Juel1)145837 |b 3 |
| 700 | 1 | _ | |a van Waasen, Stefan |0 P:(DE-Juel1)142562 |b 4 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1039472/files/ADC_MEMRISYS_2024_V2.pdf |y OpenAccess |
| 909 | C | O | |o oai:juser.fz-juelich.de:1039472 |p openaire |p open_access |p VDB |p driver |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 0 |6 P:(DE-Juel1)184396 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 1 |6 P:(DE-Juel1)159350 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 2 |6 P:(DE-Juel1)176328 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 3 |6 P:(DE-Juel1)145837 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 4 |6 P:(DE-Juel1)142562 |
| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Natural, Artificial and Cognitive Information Processing |1 G:(DE-HGF)POF4-520 |0 G:(DE-HGF)POF4-523 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Neuromorphic Computing and Network Dynamics |9 G:(DE-HGF)POF4-5234 |x 0 |
| 914 | 1 | _ | |y 2024 |
| 915 | _ | _ | |a OpenAccess |0 StatID:(DE-HGF)0510 |2 StatID |
| 920 | _ | _ | |l yes |
| 920 | 1 | _ | |0 I:(DE-Juel1)PGI-4-20110106 |k PGI-4 |l Integrated Computing Architectures |x 0 |
| 920 | 1 | _ | |0 I:(DE-Juel1)ZEA-2-20090406 |k ZEA-2 |l Zentralinstitut für Elektronik |x 1 |
| 980 | 1 | _ | |a FullTexts |
| 980 | _ | _ | |a abstract |
| 980 | _ | _ | |a VDB |
| 980 | _ | _ | |a UNRESTRICTED |
| 980 | _ | _ | |a I:(DE-Juel1)PGI-4-20110106 |
| 980 | _ | _ | |a I:(DE-Juel1)ZEA-2-20090406 |
| Library | Collection | CLSMajor | CLSMinor | Language | Author |
|---|