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@INPROCEEDINGS{Corbin:1041737,
      author       = {Corbin, Gregor and Daoud, Nour and Mohr, Bernd and De
                      Morais, Gustavo and Wolf, Felix},
      title        = {{A}re {N}oise-{R}esilient {L}ogical {T}imers {U}seful for
                      {P}erformance {A}nalysis?},
      publisher    = {IEEE},
      reportid     = {FZJ-2025-02413},
      isbn         = {979-8-3503-5554-3},
      pages        = {1519 - 1530},
      year         = {2024},
      abstract     = {In modern HPC systems, performance measurements are often
                      disturbed by noise. Because repeating measurements to
                      increase confidence in their results is costly, alternative
                      noise-resilient techniques are desirable. Therefore, we
                      implement alogical clock, which does not rely on real-time
                      measurements, in Score-P. We explore several methods to
                      model computational work with the clock increment, counting
                      OpenMP loop iterations, LLVM basic blocks/statements, or
                      hardware counters. We demonstrate the strengths and
                      weaknesses of using logical time stamps in a trace analysis
                      workflow with Score-P and Scalasca, by evaluating the
                      performanceproblems we can find in three MPI+OpenMP
                      mini-apps. By design, logical measurementsreliably show
                      algorithmic issues, such as load imbalance, but cannot
                      capture external aspects of program execution, for example
                      memory contention. In summary, logical-time based
                      measurements are a specialized but valuable addition to
                      theperformance analyst’s toolbox.},
      month         = {Nov},
      date          = {2024-11-17},
      organization  = {SC24-W: Workshops of the International
                       Conference for High Performance
                       Computing, Networking, Storage and
                       Analysis, Atlanta (GA), 17 Nov 2024 -
                       22 Nov 2024},
      cin          = {JSC},
      cid          = {I:(DE-Juel1)JSC-20090406},
      pnm          = {5111 - Domain-Specific Simulation $\&$ Data Life Cycle Labs
                      (SDLs) and Research Groups (POF4-511) / DFG project
                      G:(GEPRIS)449683531 - ExtraNoise – Leistungsanalyse von
                      HPC-Anwendungen in verrauschten Umgebungen (449683531) /
                      ATMLPP - ATML Parallel Performance (ATMLPP)},
      pid          = {G:(DE-HGF)POF4-5111 / G:(GEPRIS)449683531 /
                      G:(DE-Juel-1)ATMLPP},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      UT           = {WOS:001451792300156},
      doi          = {10.1109/SCW63240.2024.00192},
      url          = {https://juser.fz-juelich.de/record/1041737},
}